NVM 知識中心KNOWLEDGE HUB 特殊製程 eNVMSPECIALTY eNVM
研究筆記 03 · 特種半導體矽智財與高壓內嵌記憶體架構 RESEARCH NOTE 03 · SPECIALTY SILICON IP & HIGH-VOLTAGE EMBEDDED MEMORY

特種製程 NVM：類比微調、高壓顯示、矩陣修復與電子紙驅動 Specialty eNVM: Analog Trimming, HV Display, Matrix Repair & E-Ink Drivers

深入解析 BCD 電源管理（PMIC 微調、LED 驅動、USB-PD 快充協議、BLDC 馬達與 BMIC AFE）、高密集陣列缺陷修復（CIS 與 DRAM/HBM 冗餘重映射）、高壓 (HV) 顯示驅動（Gamma 2.2、Vcom、De-Mura），以及電子紙 (E-Ink) 40V-50V 超高壓電泳驅動與「演進期 MTP ➔ 成熟期 OTP」產品生命週期演進。配備 4 大旗艦級互動實驗室。 Deep treatise on BCD Power Management (PMIC trimming, LED drivers, USB-PD protocols, BLDC motor firmware, BMIC AFE), Dense Matrix Array Repair (CIS and DRAM/HBM redundancy remapping), High-Voltage Display Driver ICs, and E-Ink 40V-50V Ultra-HV driving with MTP-to-OTP lifecycle migration. Equipped with 4 flagship interactive laboratories.

原則 #01 · 邏輯 IPRULE #01 · LOGIC IP
零額外光罩0 EXTRA MASKS
純邏輯零光罩成本 PURE-LOGIC ZERO-MASK ADDER
原生 CMOS · 零高溫熱預算 Native CMOS · Zero Thermal Adder
原則 #02 · 車用RULE #02 · AUTOMOTIVE
等級 0（175°C）GRADE 0 (175°C)
車規晶圓認證閉環 SILICON QUALIFICATION RIGOR
15+ 年高溫留存 @ 175°C Tj 15+ Yrs Retention @ 175°C Tj
原則 #03 · 晶圓製程物理RULE #03 · FOUNDRY PHYSICS
4 個公式4 FORMULAS
第一性支配物理模型 FIRST-PRINCIPLES PHYSICS
帶隙 · 泊松 · 伽瑪 · 斯托克斯 Bandgap · Poisson · Gamma · Stokes
原則 #04 · DDIC 尺寸RULE #04 · DDIC PROFILE
外形尺寸 < 250 µm< 250 µm PROFILE
極窄邊框封裝約束 SLIM MACRO FORM FACTOR
COG/COF 金凸塊剪切力驗證 COG/COF Au-Bump Shear Validated
第一性原理支配物理公式 FIRST-PRINCIPLES GOVERNING PHYSICS FORMULAS

特種半導體 4 大底層物理與邊界約束 Four Governing Microphysical Models & Foundry Boundaries

公式 01EQUATION 01

01 · BANDGAP 帶隙基準溫漂模型 01 · BANDGAP Reference Temp Drift Model

VREF(T) = VBE(T) + (k T / q) · ln(N) · (R2 / R1)
一階溫漂相消條件：1st-Order Drift Cancellation: ∂VREF / ∂T = 0  |  VREF ≈ 1.205 V CTAT (−2.0 mV/°C) 與 PTAT (+0.086 mV/°C × M) 互補相消（示例係數）。AntiFuse OTP 修調電阻微調比值，消除 ±5% 製程偏差至 ±0.35%（示例修調結果，非萬能規格）。 CTAT (−2.0 mV/°C) cancels PTAT (+0.086 mV/°C × M) (illustrative coefficients). Pure-logic AntiFuse OTP tunes series R-ladder to compress ±5% raw drift down to ±0.35% (illustrative trim result, not a universal spec).
微觀物理與製程約束PHYSICS & FOUNDRY BOUNDARY BCD 高壓 DMOS 易受寄生發熱影響，零熱預算 AntiFuse 避免 eFlash 浮閘退火高溫，確保 AEC-Q100 Grade 0 (TA=150°C，極限結溫 Tj=175°C) 基準電壓長效穩定。 BCD high-voltage DMOS is sensitive to thermal budgets. Pure-logic AntiFuse eliminates eFlash anneal penalty, ensuring AEC-Q100 Grade 0 (TA=150°C, peak junction 175°C Tj) long-term stability.
公式 02EQUATION 02

02 · POISSON 泊松介電擊穿統計 02 · POISSON Dielectric Breakdown Statistics

P(k) = (λk · e−λ) / k!  |  Yrepaired = ∑k=0Nred P(k)
晶圓缺陷與擊穿機率：Defect & Breakdown Model: λ = D0 · Adie  |  F(t) = 1 − exp[−η · (t / t63)β] 在 CIS/DRAM 大面積晶粒中，缺陷服從泊松分佈。透過 BIRA 演算法與 AntiFuse OTP 硬體重映射備援行/列，以代表性大晶粒為例，修復後良率相較未修復基準 e−λ 可提升達 +55.8%（代表性基準晶粒示例；數值依晶粒面積與備援資源配置而異）。 Defect clustering obeys Poisson statistics in large CIS/DRAM dies. Remapping failed rows/columns via BIRA and AntiFuse OTP can elevate repaired yield by up to +55.8% over the unrepaired baseline e−λ in representative benchmark dies (example; subject to die area and redundancy allocation).
微觀物理與製程約束PHYSICS & FOUNDRY BOUNDARY AntiFuse 介電擊穿形成永久局域再結晶矽導電微絲 (Recrystallized Silicon Filament)，阻值自 >1011 Ω 驟降至 ∼100 Ω，無 eFuse 電遷移回跳與熱鬆弛風險。 AntiFuse dielectric breakdown forms a permanent localized recrystallized silicon filament, dropping resistance from >1011 Ω to ∼100 Ω without eFuse electromigration regrowth risks.
公式 03EQUATION 03

03 · GAMMA 2.2 亮度轉換 03 · GAMMA 2.2 Optical Transfer Function

L(V) = Lmax · [(Vgray − Vblack) / (Vwhite − Vblack)]γ  |  γ = 2.2
高壓顯示 R-DAC 灰階電壓：HV Display R-DAC Voltages: Vi = V0 + ΔV · (i / 255)1/γ ± δVtrim 人眼視覺感知符合冪律 (γ≈2.2)。HV DDIC 透過 OTP 燒錄 Gamma LUT 與 Vcom 微調值，消除面板 flicker 頻閃與 OLED 空間亮度不均 (De-Mura)。 Human vision follows power-law luminance response (γ≈2.2). HV DDIC leverages internal OTP to lock Gamma LUT & Vcom trim, eliminating flicker and OLED Mura.
微觀物理與製程約束PHYSICS & FOUNDRY BOUNDARY 高壓 18V-32V 驅動晶片要求長條形窄邊框 (<250 μm) 封裝，AntiFuse 宏單元面積遠小於 eFlash，且耐受金凸塊 COG/COF 封裝剪切應力。 HV 18V-32V DDIC imposes strict slim-border (<250 μm) form factor. AntiFuse macro occupies minimal area and survives COG/COF bonding shear stresses.
公式 04EQUATION 04

04 · STOKES 斯托克斯電泳微粒流動 04 · STOKES Electrophoretic Particle Dynamics

v = (q · E) / (6 π η r)  |  μe = q / (6 π η r)
電泳位移與溫度黏滯度關聯：Electrophoretic Drift & Viscosity: x(t) = ∫ v dt  |  η(T) ∝ exp(Ea / k T) 電子紙懸浮液中帶電顏料微粒受斯托克斯黏性阻力制約。低溫下流體黏度 η 劇增，需藉由 40V-50V 超高壓及 OTP 多溫區波形查找表 (Waveform LUT) 消除殘影。 Pigment particles in E-Ink microcapsules are governed by Stokes drag. Viscosity surges at cold temperatures, requiring 40V-50V pulses and OTP multi-temp Waveform LUTs to prevent ghosting.
微觀物理與製程約束PHYSICS & FOUNDRY BOUNDARY 超高壓 40V–50V 製程中，MTP 用於研發期波形反覆調教，成熟量產期無縫轉移至 AntiFuse OTP，單晶片成本常見可降 30% 以上（視應用／面積）且波形永久鎖定。 In 40V-50V ultra-HV nodes, MTP serves R&D waveform tuning, migrating smoothly to AntiFuse OTP in mass production to cut die cost >30% in representative cases (application/area dependent) while locking waveforms permanently.
Monolithic BCD Power Management IC (PMIC) silicon die micrograph layout showing 40V-85V LDMOS power switches, analog bandgap reference trimming circuit, AntiFuse OTP FuseBox memory array, and CMOS logic core
圖 0.1 · 單晶粒 BCD PMIC 架構 • 40V-85V LDMOS 功率級 • 類比帶隙微調 • 反熔絲 OTP 熔絲陣列 • 1mm 比例FIG 0.1 · MONOLITHIC BCD PMIC SILICON DIE ARCHITECTURE • 40V-85V LDMOS POWER STAGE • ANALOG BANDGAP TRIMMING • ANTIFUSE OTP FUSEBOX • 1mm SCALE
01 · 功率半導體與 BCD 製程整合 01 · POWER SEMICONDUCTORS & BCD INTEGRATION
量產驗證通過 PRODUCTION VERIFIED

BCD 電源管理：從低密度精準修調到高密度通訊協議韌體 BCD Power Management: Bandgap Trimming, Motor Drivers & Protocol Chips

單晶片整合 Bipolar 精度、CMOS 邏輯與 DMOS 高壓耐受力。純邏輯 AntiFuse OTP 免除浮閘 eFlash 帶來的額外熱預算，確保 40V–85V LDMOS 崩潰電壓與車規高溫可靠性。 Monolithic integration of Bipolar precision, CMOS logic, and DMOS high-voltage capability. Pure-logic AntiFuse OTP eliminates eFlash thermal budget risks, preserving 40V–85V LDMOS breakdown voltages and automotive high-temp reliability.

±0.5%
VREF 修調精度VREF TRIM ACCURACY
壓縮矽晶片原始 ±5% 帶隙漂移Tightens raw ±5% bandgap drift (illustrative example)
零光罩0 MASKS
零光罩額外成本ZERO MASK ADDER
較傳統 eFlash 省下 10~15 道光罩Saves 10-15 masks vs eFlash
175°C Tj
AEC-Q100 GRADE 0AEC-Q100 GRADE 0
永久閘極介電質擊穿微絲，耐受開關高溫Permanent gate-dielectric breakdown filament resists heat
40V–85V
LDMOS 安全工作區LDMOS SAFE-OPERATING
零熱預算衝擊，守護功率級耐壓Zero thermal impact safeguards breakdown

1.1 低密度電性微調閉迴路（128-bit ～ 2K-bit） 1.1 Low-Density Trimming Closed-Loop Pipeline (128-bit to 2K-bit)

閉迴路校準 · 漂移消除CLOSED-LOOP CALIBRATION · DRIFT CANCELLATION
圖解流程 01SLIDE FLOW 01

BCD 帶隙基準電壓 (Vref) 閉環修調時序與 AntiFuse 燒錄管線 BCD Bandgap Reference (Vref) Closed-Loop Trimming & AntiFuse Burn Pipeline

● EDA 閉迴路● EDA CLOSED-LOOP 零額外光罩0 EXTRA MASKS
EDA 時序匯流排EDA TIMING BUS
時脈：ATE_CLK 10MHzCLK: ATE_CLK 10MHz 匯流排：SAR_BUS TRIM[4:0]=10110bBUS: SAR_BUS TRIM[4:0]=10110b 脈衝：5.5V VPP @ 10µsPULSE: 5.5V VPP @ 10µs 旗標：HARD_LOCK = HIGHFLAG: HARD_LOCK = HIGH
步驟 01STEP 01 原始感測RAW SENSE
原生帶隙電壓採樣 Raw Bandgap Sense
V_RAW: 1.252V +4.2% 漂移+4.2% DRIFT
±5.0% 原始漂移±5.0% Raw Drift ATE 晶圓探針測試感測ATE PROBER CP SORT SENSE
量測PROBE晶圓針測即時捕獲CP PROBE CARD
漂移DRIFT矽摻雜高斯偏差DOPING SPREAD
▶
原始電壓RAW V
步驟 02STEP 02 SAR 邏輯SAR LOGIC
SAR 最優微調碼合成 SAR Trim Code Synthesis
TRIM[4:0] = 10110b
5 位元 SAR 梯形網路5-bit SAR Ladder 32 階二分搜尋BINARY SEARCH 32 STEPS
算法ALGORITHM逐次逼近暫存器二分求差SAR BINARY SEARCH
步階RESOLUTION1.5mV 電阻梯步階1.5mV R-LADDER
▶
SAR 編碼SAR CODE
步驟 03STEP 03 5.5V VPP 燒錄5.5V VPP ZAP
AntiFuse 物理細絲擊穿 AntiFuse Filament Rupture
5.5V @ 10µs R_FIL < 100Ω
84 Ω 導電細絲84 Ω Filament 無再生長：通過ZERO GROW-BACK PASS
機制RUPTURE閘極氧化層硬擊穿形成細絲GATE OXIDE HARD BREAKDOWN
光罩FOUNDRY MASK0 額外光罩邏輯相容ZERO MASK ADDER
▶
永久鎖定HARD LOCKED
步驟 04STEP 04 鎖定與檢查清單LOCK & CHECKLIST
電壓驗證與防篡改鎖定 Post-Trim Lock & Pass
VREF: 1.200V ±0.35% 符合規格±0.35% IN-SPEC
99.8% 良率99.8% Yield AEC-Q100 GRADE 0 (175°C)
鎖定LOCK TIMING上電 <50ns 硬體鎖死<50ns BOOT LOCK
留存RETENTION15+ 年 @ 175°C 車規耐受15+ YRS @ 175°C

1.2 高密度智慧協議與控制（高密度儲存，8KB ～ 64KB+／64Kb ～ 512Kb） 1.2 High-Density Smart Protocol & Control (8KB to 64KB+ / 64Kb to 512Kb)

韌體儲存 · MCU 整合FIRMWARE STORAGE · MCU INTEGRATION
圖解流程 01.2SLIDE FLOW 01.2

高密度智慧協議與控制：單晶片 32-bit MCU、eNVM 韌體與驅動級整合總線 Smart Protocol & Motor Control: 32-bit MCU, eNVM Firmware & Power Stage Bus

● 單晶片 BCD SoC● MONOLITHIC BCD SOC AHB／APB 交叉開關AHB/APB CROSSBAR
中央交叉開關CENTRAL CROSSBAR
核心：32 位元 RISC-V／CortexCORE: 32-BIT RISC-V / CORTEX 匯流排：零等待 AHB／APB 矩陣BUS: ZERO-WAIT AHB/APB MATRIX NVM: 16KB - 64KB (128Kb - 512Kb) MTP / OTP 功率：40V–85V 整合式 LDMOSPOWER: 40V-85V INTEGRATED LDMOS
區域 ADOMAIN A 16KB-32KB (128Kb-256Kb) MTP
USB-PD 3.1 EPR 快充控制器 USB-PD 3.1 & EPR Controller
240W (48V/5A) E-MARKER
240W 協定240W Protocol 現場線上 ISP 更新IN-FIELD ONLINE ISP PATCH
角色ROLE儲存 PDO 供電協議金鑰PDO PROFILES & KEYS
擦寫ENDURANCE10,000 次重複韌體升級10,000 CYCLES
▶
AHB BUS
區域 BDOMAIN B 32KB-64KB (256Kb-512Kb) MTP
無刷馬達向量 FOC 控制器 Brushless Motor Vector FOC
SVPWM 三相SVPWM 3-PHASE 零等待ZERO-WAIT
三相閘極驅動器3-Phase Gate Driver 換相角度 LUTCOMMUTATION ANGLE LUT
架構INTEGRATION單晶片整合三相驅動MCU + 3-PHASE DRIVER
效能LATENCY零等待匯流排調用換相ZERO-WAIT AHB LUT
▶
APB BUS
區域 CDOMAIN C Grade 0／ASIL-D（SEooC）術語，非 READY 認證Grade 0 / ASIL-D (SEooC) vocabulary — not READY cert
車規電池管理與功能安全 Automotive Battery Safety
16–24 顆電池16-24 CELLS 黑盒子BLACK-BOX
最高接面溫度 175°C175°C Tj Max Grade 0／ASIL-D（SEooC）術語之安全日誌，非 READY 認證Grade 0 / ASIL-D (SEooC) vocabulary — not READY cert SAFETY LOG
紀錄SAFETY LOG電池阻抗黑盒子查表CELL IMPEDANCE LUT
車規QUALIFICATIONAEC-Q100 Grade 0 詞彙（非認證）AEC-Q100 Grade 0 vocabulary (not a certification claim)
SEooC 假定使用 (AoU)： 可使用 ISO 26262 ASIL 詞彙（非 READY 認證）；IEC 61508 SC3 為跨標準教學對照，本頁架構不宣稱具備。LFM 等度量須以具名 FMEDA 與 Tscrub 等 AoU 關閉，不得由本頁敘述直接推出。 SEooC AoU: ISO 26262 ASIL vocabulary only (not READY certification). IEC 61508 SC3 is a cross-standard teaching reference — this page does not claim that capability by architecture alone. Metrics such as LFM require named FMEDA and AoU bounds such as Tscrub — do not infer certification from this page.
晶圓代工生態系 BCD 矩陣FOUNDRY ECOSYSTEM BCD MATRIX

BCD 製程專用 eNVM 代工生態：Tower Y-Flash、VIS/PSMC 億而得 (YMC) 與純邏輯 AntiFuse 縱深比較 Specialty BCD eNVM Foundry Matrix: Tower Y-Flash, VIS/PSMC YMC MTP & Logic AntiFuse Co-Optimization

● 特殊 BCD 與功率製程● SPECIALTY BCD & POWER 零新增光罩0 MASK ADDERS

在高壓 BCD（Bipolar-CMOS-DMOS）製程中，整合傳統雙層浮閘 eFlash 需面臨 8~12 道額外光罩與破壞功率元件耐壓的熱預算難題。業界主要 Specialty 代工廠與 IP 供應商發展出三條高度互補的 0-Mask 縱深路徑： Integrating conventional double-poly eFlash into high-voltage BCD (Bipolar-CMOS-DMOS) carries an 8-12 mask adder penalty and severe thermal budget impacts on power DMOS breakdown. Specialty foundries and IP providers have engineered three highly complementary zero-mask architectures:

Tower Semiconductor Y-Flash 零光罩 BCD 快閃記憶體0-Mask BCD Flash
製程節點：Process Node: 0.18µm BCD 與 65nm BCD 原生平台Native 0.18µm & 65nm BCD platforms
物理機制：Physics Mechanism: 單層多晶矽浮閘；Tower 公開為 CHE 寫入／BBT 抹除（非 FN/FN）Single-poly floating gate; Tower public brief: CHE program / BBT erase (not FN/FN)
耐久／留存：Endurance & Retention: 公開敘事 1K～10K cycles；Ta／Tj 與 Grade 0 資格須依具名平台分開引用Public brief cites 1K–10K cycles; cite Ta/Tj and Grade 0 qualification per named platform
高壓共存性：HV Compatibility: 零額外高溫退火，完全不影響大功率 LDMOS 擊穿電壓 (BVdss) 與導通電阻 (Ron)Zero additional thermal budget; preserves high-voltage LDMOS breakdown (BVdss) and on-resistance (Ron)
典型應用：Applications: 車用電池管理 (BMS) 電池阻抗 LUT、48V 伺服器 VRM 數位電源控制、高壓馬達驅動器Automotive BMS impedance lookup table (LUT), 48V server VRM digital power control, high-voltage motor drivers
YMC 億而得微電子 (VIS/PSMC/UMC) YMC Logic MTP / EEPROM (VIS/PSMC/UMC) 邏輯 MTP／EEPROMLogic MTP / EEPROM
製程節點：Process Node: 世界先進 VIS (0.153µm/0.18µm/0.25µm BCD)、力積電 PSMC、UMCVIS (0.153µm/0.18µm/0.25µm BCD), PSMC, UMC
物理機制：Physics Mechanism: 純邏輯 EEPROM，帶帶熱電洞注入 (BBHH) 或 FN 穿隧Standard logic EEPROM with BBHH or FN tunneling
耐久／留存：Endurance & Retention: 1K～100K cycles；10+ 年留存 @ 125°C1K-100K cycles; 10+ years retention @ 125°C
電路特點：Circuit Highlights: 內建專利微型電荷泵 (Charge Pump)，免除晶圓測試與系統端高壓 VPP 腳位負擔Integrated on-chip charge pump, eliminating external high-voltage VPP pin requirements during wafer test and in-system programming
典型應用：Applications: PMIC 基準電壓精準修調 (Vout Trim)、Type-C USB-PD 3.1 供電協議線上韌體更新、音訊 Codec 校準PMIC Vout precision trimming, Type-C USB-PD 3.1 in-field firmware updates, audio codec calibration
純邏輯 AntiFuse OTP (力旺 / Synopsys) Standard Logic AntiFuse OTP (eMemory / Synopsys) 零光罩永久型 OTP0-Mask Hard OTP
製程節點：Process Node: 全球所有主流晶圓代工廠 (TSMC, UMC, VIS, GF, Tower) 純邏輯製程Standard logic CMOS across major foundries (TSMC, UMC, VIS, GF, Tower)
物理機制：Physics Mechanism: 閘極氧化層永久性硬擊穿細絲，不可逆歐姆微絲Permanent gate oxide breakdown forming irreversible conductive ohmic filaments
耐久／留存：Endurance & Retention: 1 次寫入；>100 年留存 @ 150°C，極限結溫 175°C 無電荷洩漏風險1-time write; >100 years retention @ 150°C, zero charge-leakage risk up to 175°C Tj
安全防護：Physical Security: 無浮閘電荷，抗 X-Ray 與 UV 光照，高難度 FIB/TEM 逆向防護Zero trapped charge; immune to X-ray/UV; high resistance against FIB/TEM passive voltage contrast reverse engineering
典型應用：Applications: 帶隙基準電壓 (Bandgap Vref) 永久鎖定、晶圓識別碼 (Wafer ID)、車規黑盒子晶片序號Bandgap Vref permanent locking, Wafer ID, automotive black-box chip serials
旗艦互動實驗室 01 FLAGSHIP INTERACTIVE LAB 01

BCD 帶隙電壓微調模擬與零光罩 (Zero-Mask) 經濟學試算器 BCD Bandgap Trimming Simulator & Zero-Mask Adder ROI Calculator

左側互動體驗 OTP 微調如何消除晶圓高斯常態分佈偏差；右側 ROI 使用固定假設光罩與晶圓差價（180nm：$650K／片 $80；55nm：$1.45M／片 $180）— 非報價或量測。 Left: interactive Vref trim demo. Right: ROI uses fixed assumed mask/wafer deltas (180nm: $650K / $80 per wafer; 55nm: $1.45M / $180) — not quotes or measured savings.

1. 帶隙基準電壓 (Vref) 分佈微調模擬1. Bandgap Vref Distribution Simulation
微調前離散度Raw Variation ±4.2% (σ=1.4)
微調後收斂度Post-Trim Spread ±0.35% (σ=0.12)
規格內良率In-Spec Yield 83.5% ➔ 99.8%
2. 零光罩 (Zero-Mask) 經濟學試算器2. Zero-Mask Adder Foundry Economics 省下 10–15 層光罩10-15 MASKS SAVED
光罩費用直接節省NRE Mask Cost Saved $650,000 免除 10-14 道額外光罩費用Zero additional mask adder cost
年化晶圓代工節省Annual Wafer Savings $4,800,000 單片晶圓省 30% 且無高溫退火良率損失30% wafer cost reduction vs eFlash
圖解 01FIGURE 01 核心定理 01 · 帶隙一階溫補相消與微調幾何模型 GOVERNING PRINCIPLE 01 · BANDGAP 1ST-ORDER TEMP-COMP CANCELLATION & OTP TRIM
互補溫漂相消向量 COMPLEMENTARY DRIFT CANCELLATION
5 位元 OTP5-BIT OTP
▶
32 階二分法電阻梯微調 32-Step SAR R-Ladder Trim
高斯漂移收斂度 GAUSSIAN SPREAD CONVERGENCE
原始漂移RAW DRIFT
±5.0%
32 階 OTP 電阻微調32-STEP OTP RESISTOR TUNING
已微調TRIMMED
±0.35%
14.3× 精度提升倍率 (50ns 開機鎖定)Precision Gain (50ns Boot Locked)
溫度係數TEMPCO< 5 ppm/°C
範圍RANGE-40°C ~ 150°C Ta / 175°C Tj (AEC-Q100 Grade 0)
校準CALIBRATION零光罩 OTP 電阻梯形網路ZERO-MASK OTP R-LADDER
備援REDUNDANCY永久硬體鎖定PERMANENT HARD LOCK
電路拓樸CIRCUIT TOPOLOGY 註：一階帶隙修調拓撲採用二進制權重之串聯電阻修調梯形架構（Series Binary-Weighted R-Ladder），ΔR_OTP 為串聯微調梯階，實現高線性度 ±0.35% 精準收斂。 NOTE: First-order bandgap trimming employs a Series Binary-Weighted Resistor Ladder topology (ΔR_OTP represents series tuning increments) for high-linearity ±0.35% precision lock.
▶ 狀態契約印鑑 · 01 功率半導體與 BCD 製程整合 STATE CONTRACT TRUTH GRID · TOPIC 01
設計約定 #01 · 權責CONTRACT #01 · OWNERSHIP
50ns 開機硬體鎖定50ns BOOT HARD-LOCK
CP 測試電氣燒錄CP SORT PROG防止竄改TAMPER-PROOF
設計約定 #02 · 保存能力CONTRACT #02 · RETENTION
15+ 年 @ 175°C Tj15+ YRS @ 175°C Tj
AEC-Q100 車規結溫AEC-Q100 GRADE 0抗切換噪訊NOISE IMMUNITY
設計約定 #03 · 預算CONTRACT #03 · BUDGET
OTP 固定／MTP 可更新FIXED OTP / UPDATEABLE MTP
AntiFuse 物理擊穿ANTIFUSE BREAKDOWNNeoMTP 浮動閘可更新UPDATEABLE FLOATING-GATE NEOMTP
設計約定 #04 · 經濟效益CONTRACT #04 · ECONOMICS
0 額外光罩成本ZERO MASK ADDER
免除 10-15 道 eFlash 光罩ELIMINATES 10-15 MASKS節省百萬 NRESAVES $M NRE
矽智財選型矩陣 · BCD 電源管理內嵌記憶體架構決策 SILICON IP DECISION MATRIX · BCD POWER & PMIC 純邏輯 NVM vs 傳統浮閘 eFlash Pure-Logic NVM vs. Legacy eFlash
純邏輯 NVM 對照傳統浮閘 eFlash 決策評估矩陣Pure-Logic NVM vs. Legacy eFlash Decision Matrix
評估維度 (Metrics)Metrics & Criteria AntiFuse OTP（固定）／NeoMTP（浮動閘 MTP）Antifuse OTP (Fixed) / NeoMTP (Floating-Gate MTP) 傳統浮閘 eFlash (Floating-Gate)Legacy Floating-Gate eFlash 工程決策影響Strategic Decision Impact
額外光罩數Additional Mask Count 0 道額外光罩0 Extra Masks (Zero Adder) +10 至 +15 道光罩 (+30~50% 成本)+10 to +15 Masks (+30-50% Cost) 縮短 Tape-out 時程與原型開模費用 (NRE)Compressing prototype turnaround and tapeout NRE costs
高壓耐壓退化 (HV Impact)High-Voltage Degradation 零額外熱衝擊Zero Impact (No extra thermal budget) 製程約束 (高溫退火影響 LDMOS 漂移區耐壓)Process constraint (Thermal annealing affects LDMOS drift region) 維持 40V–85V LDMOS 崩潰電壓與 SOA 安全工作區Preserves 40V–85V breakdown voltage and Safe Operating Area (SOA)
車規高溫資料保存 (Retention)High-Temp Retention 15+ 年 @ 175°C Tj（原列選型目標，依 IP 分別驗證）；AntiFuse：擊穿路徑；NeoMTP：浮動閘電荷15+ yrs @ 175°C Tj (listed selection target; validate each IP); Antifuse: breakdown path; NeoMTP: floating-gate charge >125°C 漏電加劇 (SILC 氧化層洩漏)Degrades >125°C due to SILC oxide leakage 滿足車用動力系統與底盤 AEC-Q100 Grade 0 要求Crucial for AEC-Q100 Grade 0 automotive powertrain and chassis
超低功耗待機（待機漏電）Standby Power & Leakage < 1 pA (無接面逆向漏電)< 1 pA Zero-Junction Standby Leakage BCD 接面漏電較高 (消耗待機電流)Higher BCD junction leakage consumes standby current 賦予電子貨架標籤 (ESL) 與物聯網節點 5–10 年電池壽命Enables 5–10 year coin-cell battery lifetime for ESL and IoT nodes
前沿架構實踐 · 第三代半導體 FRONTIER PRACTICE · WIDE BANDGAP POWER

第三代半導體 SiC／GaN 閘極驅動晶片：奈秒死區微調、去飽和保護與抗 CMTI 高溫實踐 SiC/GaN Gate Drivers: Nanosecond Dead-Time Trimming, DESAT Protection & High-CMTI Resilience

在 800V 電動車主驅逆變器與 AI 伺服器高密度電源中，碳化矽 (SiC) 與氮化鎵 (GaN) 以 >500kHz 高頻開關運行。封裝極小（SOIC-8/16）的高低側隔離閘極驅動晶片（如 TI UCC217xx、Infineon EiceDRIVER™、STGAP 系列）無法容納外掛 Flash，且須在 >150 V/ns 的極端共模瞬態 (CMTI) 與 175°C 結溫下保證零失誤： In 800V EV traction inverters and AI server power units, SiC and GaN switch at >500kHz. Highly constrained isolated gate driver ICs (TI UCC217xx, Infineon EiceDRIVER™, STGAP) cannot fit external Flash and must endure >150 V/ns CMTI transients at 175°C Tj:

01 · 死區時間微調01 · DEAD-TIME TRIMMING

奈秒級死區微調：在晶圓與成測時透過片上 AntiFuse OTP 燒錄 0.5ns 步進校準碼，壓縮傳遞延遲漂移，杜絕上下橋臂直通 (Short-Through)。 Sub-nanosecond Dead-Time Trim: Calibrated via on-chip AntiFuse OTP in 0.5ns steps to eliminate propagation skew and prevent bridge cross-conduction.

02 · DESAT 閾值02 · DESAT THRESHOLD

去飽和短路保護閾值：精確微調 6V–9V 故障偵測門檻與軟關斷 (Soft Turn-Off) 電流斜率，在 2µs 內安全關斷以拯救昂貴的 SiC 功率模組。 DESAT Fault Threshold: Trims 6V–9V trip voltages and soft turn-off slew rates, securing <2µs shutdown to save expensive SiC modules.

03 · CMTI 抗擾能力03 · CMTI IMMUNITY

極端抗擾與高溫留存：AntiFuse 歐姆矽微絲具備天然抗位移電流雜訊能力；高壓 BCD Cascode 隔離免除浮閘氧化層高場擊穿老化風險。 CMTI Immunity & Retention: Ohmic filaments inherently resist displacement noise; cascode isolation protects against high-field dielectric wear.

02 · 矩陣良率與缺陷備援修復 02 · MATRIX DEFECT REPAIR & REDUNDANCY
量產驗證通過 PRODUCTION VERIFIED

高密集度矩陣修復：CIS 感光元件與 DRAM / HBM 晶圓良率守護 Dense Matrix Array Defect Repair: CIS Image Sensors & DRAM/HBM Yield Recovery

當像素陣列或記憶體單元格密度達到數千萬至數十億時，單一微塵或晶格位錯足以導致晶粒報廢。透過內建備援單元（Spare Rows / Columns）並配合 AntiFuse OTP 進行非揮發性硬體重映射，成為挽救數千億美元半導體產能的必備防線。 When pixel arrays or memory cells scale into millions and billions, a single defect causes fatal die loss. Deploying redundant spare elements and remapping defective addresses via AntiFuse OTP secures multi-billion-dollar semiconductor yields.

> 99.8%
BIST/BIRA 壞修率BIST/BIRA YIELD RECOVERY
晶圓級點缺陷與整行整列自主修復On-die point & line defect auto-repair
JEDEC PPR
JEDEC PPR 協議POST-PACKAGE REPAIR
相容 DDR5 / HBM3 硬體重映射標準JEDEC JESD79-5 / JESD238 compliant
AntiFuse
硬體反熔絲重映射HARD REPAIR VS eFUSE
高阻態轉低阻態，零高溫回跳風險Zero thermal relaxation regrowth vs eFuse
< 1.5%
陣列冗餘開銷REDUNDANCY OVERHEAD
極致矽面積開銷，換取 15-20% 良率提升Minimal area penalty for yield rescue

2.1 密集陣列自主缺陷掃描與 AntiFuse 重映射管線 2.1 Dense Array Defect Scan & AntiFuse Remap Pipeline

BIST / BIRA · 硬體修復BIST / BIRA · HARD REMAP
圖解流程 02SLIDE FLOW 02

自主缺陷檢測、備援覆蓋求解與 AntiFuse 物理重映射流程 Autonomous Defect Scan, Redundancy Solver & AntiFuse Hard Remap

● MARCH C- 10N 符合 JEDEC PPRJEDEC PPR COMPLIANT
步驟 01STEP 01 硬體 BISTHARDWARE BIST
BIST 陣列自檢雷達 BIST Radar Scan Engine
✕
March C- (10N) 定位：[第 2 列，第 1 欄]PINPOINT: [ROW 2, COL 1]
時程TIMING<50µs 全陣列遍歷<50µs FULL SCAN
捕獲FAULT LOG故障座標寫入 FIFOFIFO ADDR COORD
▶
缺陷分布FAULT MAP
步驟 02STEP 02 啟發式 BIRAHEURISTIC BIRA
BIRA 備援啟發式解算 Heuristic Greedy BIRA Solver
R₂（缺陷）R₂ (Defect)
➔
SPARE_R1
1 列額外成本1-ROW PENALTY NP 完全頂點覆蓋近似解NP-COMPLETE VERTEX COVER APPROX
算法ALGORITHM啟發式貪婪最少覆蓋 (Heuristic)HEURISTIC GREEDY MIN-COVER
挽救RECOVERY晶粒良率復原至 100%100% DIE RECOVERY
▶
燒錄訊號BURN SIG
步驟 03STEP 03 硬體固定連接HARDWIRED
AntiFuse 物理重映射 AntiFuse Hard Remap
5.5V VPP
⚡
CAM 重導CAM REDIR
R_FIL < 100 Ω 無再生長漏電ZERO GROW-BACK LEAKAGE
延遲LATENCY0-Cycle 硬體 CAM 攔截0-CYCLE CAM MATCH
留存RETENTION15+ 年 @ 175°C Tj 車規耐受15+ YRS @ 175°C Tj (AEC-Q100)
圖解 02FIGURE 02 核心定理 02 · 晶圓隨機缺陷容忍與二維備援良率救贖模型 GOVERNING PRINCIPLE 02 · WAFER DEFECT TOLERANCE & 2D SPARE YIELD RESCUE
未修復原生晶圓 (無備援) RAW WAFER (FATAL DEFECTS)
✕ ✕✕ ✕ ✕
42.8% 原生良率 (致命微塵判死)Raw Yield (Mass Scrap)
+2 備援列+2 SPARE ROWS +2 備援欄+2 SPARE COLS
▶
BIRA 最優二維重映射覆蓋 BIRA 2D Spare Redundancy Remap
AntiFuse 燒錄修復後晶圓 REPAIRED WAFER (FUSED)
✓ ✓✓ ✓ ✓
98.6% 修復後良率 (+55.8% 挽救)Repaired Yield (+55.8% Rescued)
卜瓦松良率回復POISSON RECOVERY+55.8% 良率提升+55.8% YIELD GAIN
晶粒額外面積DIE OVERHEAD< 0.18% 矽面積< 0.18% SILICON AREA
額外延遲LATENCY PENALTY0 週期 CAM 比對0-CYCLE CAM MATCH
可靠度RELIABILITY無再生長（hPPR）ZERO RE-GROWTH (hPPR)
▶ 狀態契約印鑑 · 02 矩陣良率與缺陷備援修復 STATE CONTRACT TRUTH GRID · TOPIC 02
設計約定 #01 · 永久性CONTRACT #01 · PERSISTENCE
永久重映射至備援陣列PERMANENT SPARE REMAP
CP 晶圓測試捕獲CP SORT DETECT AntiFuse 硬體燒錄ANTIFUSE OTP
設計約定 #02 · 現場 PPRCONTRACT #02 · IN-FIELD PPR
JEDEC 現場安全修復JEDEC IN-FIELD PPR
開機 BIST 授權寫入BOOT BIST ONLY 防運行中篡改RUNTIME SECURED
設計約定 #03 · 確定性CONTRACT #03 · DETERMINISM
0-Cycle 確定性硬體解碼0-CYCLE HARDWARE CAM
延遲嚴格一致 (<1.2ns)<1.2ns LATENCY 零系統停頓ZERO SYSTEM STALL
設計約定 #04 · 通道CONTRACT #04 · CHANNEL
不可逆物理閘極介電質擊穿微絲通道IRREVERSIBLE BREAKDOWN FILAMENT
擊穿阻抗 < 100ΩR_FIL < 100Ω 耐受高溫回跳ANTI-GROWBACK
旗艦互動實驗室 02 FLAGSHIP INTERACTIVE LAB 02

自主矩陣缺陷修復掃描器 Autonomous Matrix Defect Repair Simulator (BIST / BIRA / AntiFuse)

點擊下方按鈕，體驗高密度矽晶矩陣在檢測到微塵物理缺陷後，如何藉由 BIST 掃描、BIRA 解算並以反熔絲暫存器重新映射，將良率從 0% 瞬間復原至 100%。 Click controls below to simulate real-time defect detection, March C- BIST scanning, BIRA spare row/column allocation, and AntiFuse OTP burning to restore die yield from 0% to 100%.

12×12 矽晶矩陣即時狀態12×12 Silicon Matrix Array 待命狀態STANDBY
正常單元Normal Cell 物理缺陷Defect (Bad Bit) 備援重映射Spare Remapped
修復流水線控制台Repair Pipeline Console
ATE BIST／BIRA 匯流排監控ATE BIST/BIRA BUS MONITOR
> 模擬待命，等待注入缺陷…> SYSTEM READY. WAITING FOR DEFECT INJECTION...
⚡ 反熔絲硬體修復暫存器日誌 ⚡ AntiFuse Hardware FuseBox Register Map 未燒錄UNBLOWN (BLANK)
FUSE_REG[0]---（待命）--- (IDLE)空白BLANK
FUSE_REG[1]---（待命）--- (IDLE)空白BLANK
FUSE_REG[2]---（待命）--- (IDLE)空白BLANK
FUSE_REG[3]---（待命）--- (IDLE)空白BLANK
標定缺陷位址Defects Found 0
備援行/列消耗Spares Used 0 / 4
晶粒良率狀態Die Status 通過 (100%)PASS (100%)
圖解流程 02.2SLIDE FLOW 02.2

高密集陣列應用：3D 堆疊 CIS 壞點微調與 DRAM / HBM3e JEDEC hPPR 現場救援 Dense Matrix Applications: 3D-Stacked CIS Pixel Repair & HBM3e JEDEC hPPR

● TSMC 3DFABRIC JEDEC JESD238
領域 01 · 3D 感測器WING 01 · 3D SENSOR Cu-Cu 混合鍵合CU-CU HYBRID BOND
CMOS 影像感測器 (CIS) 壞點修復 CMOS Image Sensor (CIS) Pixel Repair
第 1 層：2 億畫素感測器TIER 1: 200MP PIXEL SENSOR
TSMC Cu-Cu 混合鍵合TSMC Cu-Cu HYBRID BONDING
第 2 層：ISP＋128Kb 多磁區 OTP／MTPTIER 2: ISP + 128Kb Multi-Sector OTP / MTP
128 K-bit (16 KB) LUT 晶圓測試＋現場動態熱像素重新微調CP SORT + IN-FIELD DYNAMIC HOT PIXEL RETRIM
架構ARCHITECTURE出廠靜態死點 + 運行時分區增量補償 (Multi-Sector)STATIC CP + IN-FIELD INCREMENTAL REMAP
鍵合HYBRID BOND三層晶圓垂直直接鍵合CU-CU DIRECT STACK
▶
矩陣修復MATRIX RESCUE
領域 02 · AI 記憶體WING 02 · AI MEMORY 現場 hPPRIN-FIELD hPPR
DRAM / HBM3e 封裝後現場修復 (PPR) DRAM / HBM3e Post-Package Repair (PPR)
AI XPU + HBM3e 基板堆疊AI XPU + HBM3e SUBSTRATE STACK
偵測缺陷 ➔ JEDEC hPPR 指令FAULT DETECTED ➔ JEDEC hPPR CMD
反熔絲暫存器永久重新映射ANTIFUSE FUSEBOX PERMANENT REMAP
挽救 $30,000+ 價值Salvages $30,000+ 資料中心現場零報廢ZERO FIELD SCRAP AT DATACENTER
標準STANDARD符合 JEDEC DDR5/HBM3eJEDEC JESD79-5 DDR5
現場IN-FIELD運行中在線永久修復ONLINE REPLACEMENT
圖解流程 02.3SLIDE FLOW 02.3

修復熔絲技術代際演進：雷射熔斷 ➔ 電致遷移 ➔ 反熔絲微觀擊穿細絲 Fuse Technology Evolution: Laser Fuse ➔ eFuse ➔ AntiFuse Oxide Breakdown Nanofilament

● 物理微結構● PHYSICAL MICROSTRUCTURE 無碎屑0 DEBRIS
第 1 代GEN 01 已淘汰OBSOLETE
雷射開窗物理熔斷 (Laser Fuse) Laser Ablation Fuse
開放腔體熔斷OPEN CAVITY BLAST
碎屑與濕氣風險DEBRIS & MOISTURE RISK
10 µm² 面積10 µm² Area 封裝後無法修復UNREPAIRABLE POST-PACKAGING
缺陷FATAL FLAW表面開窗致腐蝕與飛濺MOISTURE & DEBRIS
限制PACKAGING封裝後無法再次燒錄PRE-PACK ONLY
▶
演進至第 2 代GEN 2 EVOL
第 2 代GEN 02 舊式技術風險LEGACY RISKY
電致遷移電熔絲 (Poly eFuse) Electromigration eFuse
I > 10mA 形成空洞I > 10mA VOID
熱再生長風險THERMAL GROW-BACK RISK
> 10mA 驅動 FET> 10mA Drive FET 大電流驅動器成本HIGH CURRENT DRIVER PENALTY
缺陷FATAL FLAW高溫金屬回跳致位元復原THERMAL GROW-BACK
開銷LIMITATION大電流編程 FET 使每位元面積膨脹，通常僅經濟適用於 ≤4Kb–8KbBULKY PROGRAMMING FET PENALTY, UNECONOMICAL >4Kb–8Kb
▶
第 3 代奈米技術GEN 3 NANO
第 3 代GEN 03 晶圓代工標準FOUNDRY STANDARD
反熔絲閘極介電質擊穿細絲 (AntiFuse OTP) AntiFuse Dielectric Rupture Filament
R_FIL < 100 Ω
永久擊穿導電通路PERMANENT BREAKDOWN PLUG
0.5 µm² @ 0.18µm BCD 先進節點可縮小至 <0.02 µm²SCALABLE TO <0.02 µm² IN ADVANCED NODES
優勢ADVANTAGE超薄閘極硬擊穿永久熔融細絲，零回跳DIELECTRIC RUPTURE, ZERO GROW-BACK
認證FOUNDRY QUAL15+ 年 @ 175°C Tj 車規認證15+ YRS @ 175°C Tj (GRADE 0)
特殊製程價值鏈生態系 · 3D CIS 與先進記憶體修復SPECIALTY VALUE-CHAIN ECOSYSTEM · 3D CIS & ADVANCED MEMORY REPAIR

3D 堆疊 CIS 像素修補與 HBM3/DDR5 JEDEC PPR 硬體重映射實踐 3D-Stacked CIS Defect Repair & HBM3/DDR5 JEDEC PPR Silicon Implementation

Sony / OmniVision 3D 背照式 CIS 像素修補 Sony / OmniVision 3D BSI CIS Pixel Repair

Cu-Cu DBI 鍵合Cu-Cu DBI Bonded

感光像素晶粒與邏輯晶粒透過 Cu-Cu 混合鍵合 (DBI) 堆疊。晶圓測試 (CP) 時檢測出成千上萬個暗電流亮點 (Hot Pixels)。嚴禁採用傳統 eFlash：因 >900°C 退火會熔毀已塗佈之彩色濾光片與微透鏡；嚴禁雷射熔斷：因封裝後雷射無法穿透矽層。常見架構為 0-Mask 純邏輯 AntiFuse OTP，在室溫探針測試下以電氣脈衝硬鎖定數十 Kb 壞點座標 — 具名產品仍須對照 PDK 與修復流程，非全族唯一解。 Pixel dies bond to logic dies via Cu-Cu DBI. Testing flags thousands of hot pixels. eFlash is forbidden as >900°C anneal destroys color filters and microlenses; laser fuses are inaccessible inside stacked 3D dies. A common architecture is zero-mask logic AntiFuse OTP that electrically locks defect coordinates at room temperature — named products still need PDK/repair-flow evidence; not a universal-only solution.

JEDEC DDR5 / HBM3 Hard-PPR 封裝後修復 JEDEC DDR5 / HBM3 Hard-PPR Post-Package Repair

JESD79-5 / JESD238

JEDEC 標準定義了封裝後硬體重映射 (Hard Post-Package Repair, hPPR)。傳統 Poly eFuse 因電致遷移空隙具備熱鬆弛回跳 (Grow-Back) 致命缺陷，在伺服器高溫環境下易使已修復壞位元死灰復燃；而 AntiFuse 的局域再結晶矽微絲為永久性歐姆通道 (R < 100Ω)，在 150°C~175°C 高溫下具備零回跳與永久性物理鎖定，成為高頻寬記憶體 (HBM3/HBM3e) 與 DDR5 模組良率的產業黃金基準。 JEDEC defines Hard Post-Package Repair (hPPR). Conventional poly eFuses suffer thermal grow-back, risking defect reappearance under server heat. AntiFuse forms permanent recrystallized ohmic silicon filaments (R < 100Ω) with zero grow-back across 150°C~175°C, serving as the gold standard for DDR5 and HBM3 stack yields.

03 · 顯示面板與光電驅動 (HV DDIC) 03 · HIGH-VOLTAGE DISPLAY DRIVERS & OPTICS
量產驗證通過 PRODUCTION VERIFIED

高壓顯示驅動 (HV DDIC)：Gamma 校準、Vcom 防閃爍與 De-Mura 補償 High-Voltage Display Drivers: Gamma Tuning, Vcom Anti-Flicker & De-Mura

顯示面板驅動 IC（DDIC）整合了雙重耐壓域：高壓端 Gate Driver 承受高達 35Vp-p 峰對峰擺幅（V_GH = +20V, V_GL = -15V，製程耐壓安全裕度達 40V），類比端 Source Driver 則為高速高精度 8V ~ 12V（AMOLED 子像素驅動可達 16V）。內嵌 eNVM 必須在嚴苛的高壓環境中長期抵抗電氣干擾，精準儲存光學校準參數與灰階查找表。 Display Driver ICs (DDICs) partition into dual voltage domains: Gate Drivers handle 35Vp-p swings (V_GH = +20V, V_GL = -15V with 40V process breakdown margin), while Source Drivers operate at 8V~12V (up to 16V for AMOLED sub-pixels). Embedded eNVM must withstand high-voltage electrical stress to preserve optical calibration registers and color correction tables.

10 位元10-BIT
GAMMA 2.2 精度GAMMA 2.2 ACCURACY
1024 階高壓階梯補償，精準匹配面板光學1024-step high-voltage DAC compensation
逐點Point-by-Point
DE-MURA 補償矩陣DE-MURA CALIBRATION
逐點光學微調，消弭 AMOLED 亮度與色彩斑塊Eliminates AMOLED brightness & color mura
35Vp-p / 40V
Gate 擺幅與製程耐壓GATE SWING & PROCESS MARGIN
Gate 峰對峰 35V (+20V/-15V) · 40V 耐壓裕度 · Source 端 8-12VGate 35Vp-p (+20V/-15V) · 40V margin · Source 8-12V analog rail
+18%
驅動能效增益DRIVER POWER EFFICIENCY
智慧電壓調製與零靜態漏電架構Smart voltage modulation & zero-leakage architecture

3.1 高壓顯示光學補償與 Gamma 校準管線 3.1 High-Voltage Display Optical Compensation & Gamma Pipeline

光學訊號鏈 · 閉環微調OPTICAL SIGNAL CHAIN · CLOSED-LOOP TRIM
圖解流程 03SLIDE FLOW 03

高壓顯示面板光學訊號鏈：Vcom 防閃爍 ➔ Gamma 2.2 R-DAC ➔ OLED De-Mura 補償 Display Optical Signal Chain: Vcom Centering ➔ Gamma 2.2 R-DAC ➔ 2D De-Mura Compensation

● 光學訊號鏈● OPTICAL SIGNAL CHAIN DELTA E < 1.0
階段 01STAGE 01 抗閃爍ANTI-FLICKER
Vcom 共同電極中心微調 Vcom Center Calibration
±5mV 步階±5mV STEP 0Hz 黏滯0Hz STICKING
5mV 精細步階5mV Fine Step 零直流極化偏壓ZERO DC POLARIZATION BIAS
目標TARGET消除液晶殘留直流偏壓ZERO DC BIAS (0Hz)
規格STORAGE7-bit 至 10-bit OTP 鎖定7-10 BIT OTP LOCK
▶
Vcom 通過VCOM OK
階段 02STAGE 02 10 位元精度10-BIT PRECISION
Gamma 2.2 階梯 R-DAC 映射 Gamma 2.2 R-DAC Curve
1024 階 DAC1024-STEP DAC ΔE < 0.8
1024 階1024 Levels 非線性光學匹配NON-LINEAR OPTICAL MATCH
分壓HV ARCH高壓階梯分壓擬合人眼1024-STEP R-DAC
色階PRECISION色階均勻平滑無斷階DELTA E < 1.5
▶
Gamma 通過GAMMA OK
階段 03STAGE 03 OLED 2D MURA
OLED 2D De-Mura 空間補償 2D OLED De-Mura Compensation
均勻度：98.6%UNIFORMITY: 98.6% MTP LUT
74% ➔ 98.6% 全螢幕均勻度提升FULL SCREEN UNIFORMITY GAIN
機制MECHANISM像素級增益查找表平坦化2D PIXEL GAIN LUT
架構FLASHLESS內嵌 MTP 免外掛 FlashZERO SPI FLASH BOM
圖解 03FIGURE 03 核心定理 03 · 人眼光學非線性感知曲線與 2D DE-MURA 補償 GOVERNING PRINCIPLE 03 · OPTICAL GAMMA 2.2 TRANSFER & 2D DE-MURA FLATTENING
人眼感知光電非線性曲線 PERCEPTUAL GAMMA 2.20 CURVE
32 K-bit (4 KB) MTP
▶
2D 像素增益矩陣查表 2D Pixel Gain Matrix LUT
空間均勻度平坦化對比 SPATIAL UNIFORMITY FLATTENING
原始 Mura（ΔE 3.82）RAW MURA (ΔE 3.82)
76.4% 均勻度76.4% UNIFORMITY
➔
已校準（ΔE < 0.8）CALIBRATED (ΔE < 0.8)
99.2% 均勻度99.2% UNIFORMITY
光學精度OPTICAL PRECISIONΔE < 0.8（無 Mura）ΔE < 0.8 (ZERO MURA)
Vcom 精確度VCOM ACCURACY±5mV 中心電壓（0Hz 黏滯）±5mV CENTER (0Hz STICKING)
DAC 解析度DAC RESOLUTION10 位元（1024 階）10-BIT (1024 LEVELS)
BOM 優勢BOM ADVANTAGE無快閃記憶體 COG／COF（<250μm）FLASHLESS COG/COF (<250μm)
▶ 狀態契約印鑑 · 03 高壓顯示驅動與光學微調 STATE CONTRACT TRUTH GRID · TOPIC 03
設計約定 #01 · 光學CONTRACT #01 · OPTICAL
模組點燈段寫入MODULE TEST BURN
De-Mura 補償表DE-MURA LUTVcom 中心電壓鎖定VCOM LOCKED
設計約定 #02 · 無快閃記憶體CONTRACT #02 · FLASHLESS
無外掛 Flash (Flashless)FLASHLESS BOM
節省 PCB 與 BOM 面積SAVES PCB SPACE消除 SPI 通訊 EMIZERO SPI EMI
設計約定 #03 · 更新CONTRACT #03 · REFRESH
開機自動載入驅動暫存器AUTO-SHADOW AT BOOT
同位元檢查防護PARITY CHECK防止高壓噪訊撕裂TEAR-FREE HV
設計約定 #04 · 封裝CONTRACT #04 · PACKAGING
COG/COF 極致長寬比COG/COF FORM FACTOR
< 250µm 巨集高度<250µm PROFILE金凸塊剪切應力認證AU-BUMP SHEAR CERT
旗艦互動實驗室 03 FLAGSHIP INTERACTIVE LAB 03

高壓顯示光學調節器 (Gamma 2.2、Vcom 頻閃消除與 De-Mura 補償) High-Voltage Display Optical Tuner (Gamma 2.2, Vcom Anti-Flicker & De-Mura)

左側滑動調節 Gamma 曲線與觀察色階輸出；右側 De-Mura 均勻度／ΔE 為固定假設示意（74.2%→99.4%、3.8→0.45），非光學量測。 Left: Gamma curve tuner. Right: De-Mura uniformity/ΔE uses fixed teaching assumptions (74.2%→99.4%, 3.8→0.45) — not optical measurement.

1. Gamma 2.2 曲線微調面板1. Gamma Curve & Vcom Calibration Gamma: 2.20
即時 256 階灰階色階響應Real-time 256-level greyscale response
2. OLED De-Mura 像素均勻度視覺對比2. OLED De-Mura Uniformity Comparator
光學均勻度（固定假設）Uniformity (fixed assumption) 74.2%（示意 · 非量測）74.2% (illustrative · not measured)
色偏 ΔE（固定假設）ΔE (fixed assumption) 3.8（示意 · 非量測）3.8 (illustrative · not measured)
NVM 查表狀態NVM Status 未啟用補償BYPASS
硬體矽智財認證規範 · 晶圓特性化與量產門檻 SILICON IP CHARACTERIZATION & QUALIFICATION DISCIPLINE
實體矽驗證準則 SILICON-PROVEN RIGOR

高壓與特種製程 Hard IP：從測試晶片流片到車規可靠度封閉全流程 High-Voltage Hard IP Rigor: From Test Chip Tapeout to Reliability checklist

NVM 是極度敏感的實體 Hard IP，絕非可任意合成轉移的軟體 RTL。代工廠具備特定高壓或特種製程，絕不代表矽智財廠商已有現成 Macro 布局。每一個特定金屬層堆疊（Metal Stack）與 PDK 變體，均必須歷經獨立的專屬測試晶片（Test Chip）流片、全溫區 PVT Corner 特性化實測與車規級加速老化驗證。 Embedded NVM is custom physical Hard IP, not portable generic RTL. A foundry offering a specialty process does NOT imply Silicon IP availability. Every specific metal stack and PDK variant mandates dedicated test chip tapeouts, multi-lot PVT corner characterization, and automotive reliability checklist.

晶圓製程驗證FOUNDRY RIGOR 三階段晶片檢查關卡3-STAGE SILICON CHECKLIST GATES

特種高壓製程實體 IP 晶圓驗證三道簽核流程 Specialty HV Hard IP Silicon verification checklist pipeline

NVM 為客製實體 Hard IP，非軟體 RTL。每一 PDK 變體必須嚴格通過三道實體晶圓門禁簽核： Embedded NVM is custom physical Hard IP. Every PDK variant mandates 3 silicon verification checklist gates:

✓ 關卡 01 已簽核GATE 01 SIGNED-OFF
PVT SHMOO
PPP PPP PPP
階段 01 · 實體流片與特性化PHASE 01 · TEST CHIP & CHAR

3-Lot 晶圓流片與 Shmoo 裕度3-Lot Tapeout & Shmoo Matrix

  • 晶圓批次：Wafer Lots: 專屬測試晶片跨 3 批次 (3-Lot)Dedicated 3-Lot test vehicles
  • 溫度跨度：Temp Range: -40°C ~ 150°C / 175°C
  • 電壓裕度：Voltage: ±10% VDD Core / IO Shmoo
  • 物理指標：Physical: 細絲電阻 <100Ω 4σ 分佈Filament R < 100Ω 4σ fit
▶
✓ 關卡 02 已簽核GATE 02 SIGNED-OFF
+20V/-15V dV/dt
150°C 1000h HTOL
階段 02 · 高壓瞬態與可靠度PHASE 02 · TRANSIENT & QUAL

高壓脈衝隔離與 HTOL 老化HV Noise Isolation & HTOL Qual

  • 隔離架構：Isolation: Deep N-Well 三重基板保護環Deep N-Well guard-rings
  • 耐受指標：dV/dt: 50V/ns 高速瞬態脈衝抑制50V/ns pulse suppression
  • 加速老化：Stress: 1000 小時 HTOL + HTSL 烘烤1000h HTOL + HTSL bake
  • 電荷保存：Retention: 消除浮閘 SILC 電荷流失路徑；關斷漏電 <0.1 pA/cell，15+ 年 @ 175°C TjEliminates floating-gate SILC loss path; standby leakage <0.1 pA/cell, 15+ yrs @ 175°C Tj
▶
✓ 關卡 03 已簽核GATE 03 SIGNED-OFF
<250μm
260°C 無鉛回焊Pb-Free Reflow
階段 03 · 封裝熱機械應力PHASE 03 · PACKAGING & FORM FACTOR

COG/COF 金凸塊與 260°C 迴焊COG/COF Au-Bumps & Reflow

  • 幾何極限：Form Factor: Macro 高度嚴格限制 <250μmMacro height < 250μm
  • 晶圓薄化：Thinning: 打薄至 <100μm 應力無裂紋Thinning <100μm zero crack
  • 接合剪切：Shear: Au-bump 剪切力 >15g/mil²Au-bump shear > 15g/mil²
  • 熱應力：Reflow: J-STD-020 260°C 無鉛迴焊通過J-STD-020 260°C reflow pass
顯示驅動生態系 · AMOLED De-Mura 與先進封裝DISPLAY DRIVER ECOSYSTEM · AMOLED DE-MURA & ADVANCED PACKAGING

OLED 顯示驅動 (DDIC) 逐點 De-Mura 光學補償與超低引腳數外掛 NOR 封裝革新 AMOLED DDIC Point-by-Point De-Mura & Ultra-Low Pin Count Serial NOR Innovation

Novatek / Himax AMOLED De-Mura 數據暴增挑戰 Novatek / Himax AMOLED De-Mura Data Scaling Challenge

FHD+／WQHD+ 二維網格FHD+ / WQHD+ 2D Grid

高階 AMOLED 面板由於有機發光材料沉積的不均勻性，需外置相機高精掃描並生成 2D 亮度/色度差分補償矩陣 (De-Mura)。隨面板解析度自 FHD+ 提升至 WQHD+，De-Mura 數據量自數十 KB 暴增至 4MB~16MB。若將其全部內嵌於高壓製程 (28nm/40nm HV) 晶粒內，高壓 eFlash 面積開銷過巨，將嚴重損害 DDIC 長條形晶粒 (Aspect Ratio > 20:1) 的良率與晶圓產出。 AMOLED panels exhibit pixel luminance variations requiring factory optical scanning to generate 2D De-Mura matrices. As resolutions reach WQHD+, De-Mura data explodes from tens of KB to 4MB~16MB. Monolithically embedding this into 28nm/40nm HV DDIC dies inflates silicon area, devastating yields for ultra-narrow aspect ratio (>20:1) dies.

內部 0-Mask OTP + 外部/合封 Ultra-Low-Pin NOR 雙軌解法 Internal 0-Mask OTP + External Ultra-Low-Pin NOR Hybrid Route

WLCSP / USON / Octal SPI

產業主流轉向分層儲存：核心電氣參數 (Vcom、Gamma 曲線、晶片安全 ID) 採用晶片內 0-Mask 純邏輯 AntiFuse OTP / MTP 永久硬鎖定，抵抗高壓電氣雜訊；龐大之 De-Mura 點矩陣 則透過高速 Octal SPI / xSPI 介面串接外掛或 COF (Chip-on-Film) 上合封之 Winbond / Macronix 1.2V 超低引腳數 Serial NOR Flash (WLCSP 或超薄 USON 封裝)，於開機時極速 DMA 載入內部 SRAM，兼顧極致窄邊框與最低系統 BOM 成本。 Industry adopts a tiered hybrid: Critical electrical parameters (Vcom, Gamma, security ID) are locked on-chip via 0-mask logic AntiFuse OTP/MTP against HV noise; massive 2D De-Mura matrices stream via high-speed Octal SPI from co-packaged Winbond/Macronix 1.2V ultra-low-pin Serial NOR Flash (WLCSP/USON on COF), balancing razor-thin display borders with optimal BOM.

04 · 電子紙與超高壓電泳驅動 04 · ULTRA-HV E-PAPER & ELECTROPHORETIC DRIVING
量產驗證通過 PRODUCTION VERIFIED

電子紙 (E-Ink) 超高壓驅動：40V-50V 脈衝波形與 MTP ➔ OTP 演進 E-Ink Ultra-HV Driving: 40V-50V Waveforms & MTP-to-OTP Migration

雙穩態電泳顯示（EPD）憑藉超低功耗與陽光下高可讀性，已橫掃電子貨架標籤（ESL）與電子閱讀器市場。然而，驅動微膠囊中帶電色素微粒子需要高達 40V 至 50V 的超高壓雙極性脈衝。 Bistable electrophoretic displays (EPD) dominate Electronic Shelf Labels (ESL) and e-readers through near-zero static power. However, moving charged pigment particles inside microcapsules demands 40V to 50V ultra-high-voltage bipolar pulses.

40V–50V
超高壓驅動軌ULTRA-HV RAIL VOLTAGE
克服微膠囊高黏度流體剪切阻力Overcomes viscous electrophoretic shear drag
0 W
雙穩態靜態功耗BISTABLE STANDBY POWER
雙穩態粒子鎖定，畫面靜止零耗電Zero static power in bistable resting state
-15°C~65°C
多色查表溫域MULTI-COLOR LUT RANGE
多色粒子 Spectra/Kaleido 全溫域驅動查表Wide-temp range multi-color waveform tables
MTP ➔ OTP
生命週期成本遷移LIFECYCLE COST SHIFT
演進期多重調校至成熟期零光罩成本節省 35%Eliminates mask costs saving 35% wafer price

4.1 超高壓電泳波形時序與雙穩態狀態機 4.1 Ultra-HV Electrophoretic Timing & Bistable State Machine

40V-50V 波形 · 雙穩態驅動40V-50V WAVEFORM · BISTABLE DRIVER
圖解流程 04SLIDE FLOW 04

40V-50V 雙極性電泳驅動波形時序與 MTP ➔ OTP 產品生命週期狀態機 40V-50V Bipolar Electrophoretic Waveform Timing & MTP-to-OTP State Machine

● 40V–50V 雙極● 40V-50V BIPOLAR 0W 雙穩態靜止0W BISTABLE REST
波形階段WAVEFORM PHASES
階段 A：震盪（±15V）PHASE A: SHAKE (±15V) 階段 B：重置（-40V）PHASE B: RESET (-40V) 階段 C：驅動（+40V~+50V）PHASE C: DRIVE (+40V~+50V) 階段 D：雙穩態靜止（0V／0W）PHASE D: BISTABLE REST (0V / 0W)
階段 A／BPHASE A / B 粒子流體力學PARTICLE FLUIDICS
微粒活化與殘影擦除 (Shake & Reset) Agitation & Erase Pulse
±15V 震盪 ➔ -40V 重置±15V SHAKE ➔ -40V RESET
克服黏滯阻力OVERCOMES VISCOUS DRAG
-40V 清除電源-40V Erase Rail 消除殘影GHOSTING CANCELLATION
物理PHYSICS克服微膠囊微粒靜摩擦力OVERCOME FRICTION
基線BASELINE帶電微粒拉回初始底板COMMON RESET (-40V)
▶
已清除ERASED
階段 C／DPHASE C / D 目標與靜止TARGET & REST
目標推升與雙穩態休眠 (Drive & Rest) Target Drive & Bistable Rest
+40V~+50V 驅動 ➔ 0V 靜止+40V~+50V DRIVE ➔ 0V REST
零靜態功耗ZERO STATIC POWER DRAIN
0W 待機功耗0W Standby Power 10 年電池壽命10-YEAR BATTERY LIFETIME
脈衝HV PULSE40V-50V 快速電泳遷移40V-50V (<200ms)
保持BISTABILITY斷電畫面永久保持 10 年0W POWER HOLD
▶
生命週期LIFECYCLE
狀態機STATE MACHINE MTP ➔ OTP 轉換MTP ➔ OTP SHIFT
eNVM 產品生命週期演進 MTP to OTP Migration
MTP（研發）➔ OTP（量產）MTP (R&D) ➔ OTP (VOLUME)
晶圓成本降低 35%35% WAFER COST REDUCTION
高度 < 250 µm< 250 µm Height 超薄 DDIC 外形尺寸ULTRA-SLIM DDIC FORM FACTOR
開拓ERA 01 MTP支援多次在線波形微調32Kb-64Kb TUNABLE
成熟ERA 02 OTP配方穩定後切入邏輯 OTPZERO-MASK ANTIFUSE
Ultra-High-Voltage E-Paper Display Driver IC (DDIC) silicon die layout showing 40V-50V HV level shifters, dynamic Waveform Look-Up Table (Waveform LUT) MTP/OTP memory, and peripheral gold bumping pads for COG/COF bonding
圖 4.1 · 超高壓電子紙顯示驅動晶片 (DDIC) • 40V-50V 源極驅動器 • 波形查找表 (MTP/OTP) • <250μm 厚度 • COG/COF 金凸塊接墊FIG 4.1 · ULTRA-HV E-INK DISPLAY DRIVER IC (DDIC) SILICON DIE • 40V-50V SOURCE DRIVERS • WAVEFORM LUT (MTP/OTP) • <250μm PROFILE • COG/COF Au-BUMP PADS
圖解 04FIGURE 04 核心定理 04 · 微膠囊雙穩態電泳動力學與零功耗靜態保持 GOVERNING PRINCIPLE 04 · BISTABLE ELECTROPHORETIC KINETICS & ZERO-POWER RETENTION
電壓 vs 粒子移徙速度階躍 RAIL VOLTAGE VS PARTICLE VELOCITY
5V 標準邏輯5V STD LOGIC 25 μm/s
>1800ms 延遲（嚴重殘影）>1800ms LAG (FATAL RESIDUAL)
50V 超高壓50V ULTRA-HV 250 μm/s
<180ms 更新（加速 10 倍）<180ms REFRESH (10× SPEEDUP)
+50V 頂部（白色）+50V TOP (WHITE)
+++
⇵ 斯托克斯流體 η⇵ STOKES FLUID η
---
-50V 底部（黑色）-50V BOTTOM (BLACK)
微膠囊（d=40μm）MICROCAPSULE (d=40μm)
斷電零漏電雙穩態保持 POWER-OFF BISTABLE RETENTION
0.00 μW 靜態待機功耗（0A 電流）STATIC STANDBY POWER (0A DRAIN)
🔒 影像保存超過 10 年10+ YEARS IMAGE PERSISTENCE
驅動電壓DRIVE VOLTAGE40V–50V 雙極電源40V - 50V BIPOLAR RAIL
轉換時間TRANSIT TIME<200ms 高速更新< 200ms HIGH-SPEED REFRESH
待機功耗STANDBY POWER0W／0A（真正雙穩態）0W / 0A (TRUE BISTABILITY)
儲存媒介STORAGE MEDIUMMTP ➔ 零光罩 OTP 演進MTP ➔ ZERO-MASK OTP EVOLUTION
斯托克斯動力學STOKES KINETICS 推導閉環：粒子移徙速度 v = (q · E) / (6πηr)，電場 E = Vrail / dcell = 50 V / 40 μm = 1.25 × 106 V/m，50V 超高壓電場以 10× 加速比克服微膠囊流體黏滯阻力 (η)。 PHYSICS CLOSURE: Drift velocity v = (q · E) / (6πηr), where E = Vrail / dcell = 50 V / 40 μm = 1.25 × 106 V/m; 50V ultra-HV delivers a 10× speedup to overcome fluid drag (η) under 200ms.
▶ 狀態契約印鑑 · 04 電子紙與超高壓電泳驅動 STATE CONTRACT TRUTH GRID · TOPIC 04
設計約定 #01 · 波形CONTRACT #01 · WAVEFORM
原廠授權波形鎖死LOCKED WAVEFORM
微膠囊壽命保護CAPSULE LIFETIMEOTP/MTP 物理防護PHYSICAL LOCK
設計約定 #02 · 熱特性CONTRACT #02 · THERMAL
即時溫度查表補償REAL-TIME TEMP COMP
-15°C ~ 65°C 消除殘影-15°C~65°C GHOST-FREE動態脈衝序列DYNAMIC PULSE SEQ
設計約定 #03 · 生命週期CONTRACT #03 · LIFECYCLE
MTP ➔ OTP 平滑演進MTP-TO-OTP MIGRATION
開拓期 MTP 微調波形MTP TUNING PHASE成熟期 AntiFuse 省 35%OTP SAVES 35% BOM
設計約定 #04 · 零功耗CONTRACT #04 · ZERO-DRAIN
0.00 µW 零待機功耗0.00 µW ZERO STANDBY
雙穩態粒子靜止保持BISTABLE PERSISTENCE10 年電池壽命10-YEAR BATTERY
旗艦互動實驗室 04 FLAGSHIP INTERACTIVE LAB 04

電子紙微膠囊電泳物理與高壓波形示波器 E-Ink Electrophoretic Physics & High-Voltage Waveform Oscilloscope

切換不同顯示模式，觀察微膠囊中帶電色素微粒子的受力沉浮過程、實時示波器 40V-50V 驅動脈衝序列，以及對應的 MTP ➔ OTP 演進決策。 Switch display modes to witness charged pigment microparticle migration under 40V-50V pulses, real-time waveform oscillograms, and MTP-to-OTP architecture migration indicators.

1. 微膠囊粒子電泳斷面模擬1. Microcapsule Particle Migration 黑白快速更新MONO FAST REFRESH
2. 40V-50V 驅動波形示波器與 eNVM 演進狀態2. Driving Waveform Pulse & eNVM Lifecycle ±15V 脈衝±15V PULSE
階段 A：±15V 震盪（40ms）Phase A: ±15V Shake (40ms) → 階段 B：-15V 清除（60ms）Phase B: -15V Clear (60ms) → 階段 C：+15V 驅動（100ms）Phase C: +15V Drive (100ms)
當前架構決策階段：Architectural Phase: MTP 使用中（轉換期）MTP ACTIVE (TRANSITION ERA)

彩色粒子配方與微膠囊製程快速疊代演進中。採用 32 K-bit ～ 64 K-bit (4 KB ～ 8 KB) MTP 保持在線波形查表 (LUT) 更新彈性。 Color particle formulation is evolving. Deploying 32 K-bit to 64 K-bit (4 KB to 8 KB) MTP ensures flexibility for in-field waveform LUT updates.

波形查表需求LUT Footprint: 32 K-bit (4 KB)
晶粒巨集高度Macro Height: <250 μm（已最佳化）<250 μm (Optimized)
顯示架構對比矩陣 · 電子紙 vs 傳統液晶/有機發光 DISPLAY ARCHITECTURE MATRIX · E-INK VS. LCD/OLED 雙穩態超高壓電泳 vs 連續供電發光 Bistable Ultra-HV Electrophoretic vs. Active Emissive
雙穩態超高壓電泳對照主動發光顯示比較矩陣Bistable Ultra-HV Electrophoretic vs. Active Emissive Comparison Matrix
比較維度 (Factor / Feature)Factor / Feature 電子紙 (E-Ink / EPD)E-Ink / EPD 液晶與有機發光 (LCD / OLED)LCD / OLED 驅動晶片與 eNVM 關鍵意涵DDIC & eNVM Strategic Impact
畫面動態更新Motion Display 偏慢 (數百毫秒粒子電泳)Slow (Hundreds of ms particle migration) 即時 (60Hz - 144Hz 更新率)Real-time (60Hz - 144Hz refresh rate) 電子紙需要依據溫度調用多幀波形序列 (Waveform Frames)E-Ink requires temperature-dependent multi-frame waveform lookups
能源消耗特性Energy Consumption 雙穩態 (僅在畫面更新時耗電)Bistable (Power only at content change) 持續耗電 (需背光或持續驅動電流)Constant power draw (Continuous backlight/current) 極低待機漏電；以內嵌 eNVM 取代離散 Flash 降低系統待機功耗Low standby leakage; embedded eNVM replaces external Flash to reduce standby draw
驅動電壓水準Drive Voltage Rails 40V 至 50V 雙極性電泳脈衝40V to 50V Bipolar Electrophoretic Pulse Gate 35Vp-p (+20V/-15V) / Source 8V-16V (40V 製程裕度)Gate 35Vp-p (+20V/-15V) / Source 8V-16V (40V Process Margin) 受限 COG/COF 極致長寬比 (<250µm) 與多通道高密度，BCD 製程在尺寸與金屬層數上受限，採用專屬 110HV / 90HV 高壓 CMOSDue to ultra-slim die aspect ratio (<250µm for COG/COF) and high channel density, BCD is constrained by layout; mandates dedicated 110HV/90HV High-Voltage CMOS
全彩顯示能力Full Color Capability 演進中 (黑白 ➔ 4 色 ➔ Spectra 6 / Kaleido 3)Evolving (Mono ➔ 4-Color ➔ Spectra 6 / Kaleido 3) 純熟原生全彩 (RGB 16.7M 色以上)Mature native full color (16.7M+ colors) 演進期以 32 K-bit ～ 64 K-bit (4 KB ～ 8 KB) MTP 保持波形更動彈性，成熟後轉入低成本 OTP32-64 K-bit (4-8 KB) MTP ensures code flexibility during color evolution; OTP for mature high volume
環境強光可讀性Sunlight Readability 優良環境光對比 (反射式架構，陽光下保持可讀)High ambient contrast (Reflective; readable under direct sunlight) 對比度受限 (需提高背光亮度對抗強光反射)Contrast reduced (Requires increased backlight brightness to overcome ambient light) 大型戶外公車站看板需串聯更多顆 Driver ICLarge outdoor signage cascades numerous driver ICs, multiplying NVM TAM
核心應用場景Key Applications ESL 電子貨架標籤、電子書、戶外全彩廣告牌、車身/建築裝飾 (Prism 3)ESL electronic shelf labels, e-readers, outdoor color billboards, Prism 3 automotive skins 智慧手機、筆電、電視、車用儀表座艙Smartphones, laptops, TVs, automotive digital cockpits 電子紙市場年複合成長率 (CAGR) 顯著，帶動特種 eHV eNVM 需求擴展E-paper market CAGR expands specialty eHV eNVM demand across retail and outdoor infrastructure