架構權衡天平 · 技術基礎 F2ARCHITECTURAL TRADE-OFF BALANCER · FOUNDATION F2

NVM 技術全景對比：架構比對天平 NVM Technology Trade-Off: Architectural Matrix

依 5 族 NVM（晶圓代工製程方案；OTP：FG-OTP vs AntiFuse；MTP：LD vs HD；eFlash：SST vs SONOS；Emerging：ReRAM/MRAM）的 11 把技術葉，在 9 維比較維度上做系統架構橫向比對；並結合隧道物理、晶圓成本與代工 PDK 現況。具名 IP（Actt LogicFlash、NSCore TwinBit、Floadia ZT／ZA／G1／G2、CFX、Attopsemi I-fuse、SST SuperFlash）掛在既有族群葉下，機制不同者不合併。公開來源表述多數原則，非無偏見天平。 Systematic architectural cross-examination across 5 NVM family buckets (Foundry process solutions; OTP with FG-OTP vs AntiFuse; MTP with LD vs HD; eFlash SST vs SONOS; Emerging ReRAM/MRAM) covering 11 technology leaves on 9 comparison dimensions, plus tunneling physics, wafer-cost economics, and foundry PDK realities. Named IPs (Actt LogicFlash, NSCore TwinBit, Floadia ZT/ZA/G1/G2, CFX, Attopsemi I-fuse, SST SuperFlash) sit under existing family leaves and are not merged across distinct mechanisms. Grounded in public sources and majority-principle framing — not an unbiased oracle.

5 大家族5 BUCKETS Sam 家族分組Sam Family Taxonomy

11 類技術11 LEAVES 獨立技術欄位Distinct Columns

0 道光罩0 MASK 邏輯相容極限Logic Adders

4 大代工4 FOUNDRIES 晶圓生態驗證Foundry PDKs

法則 #01 · 光罩開銷RULE #01 · MASK OVERHEAD

0 道額外光罩0 MASK ADDERS

邏輯相容光罩模型 LOGIC-COMPATIBLE MASK MODEL

零額外光罩 ≠ 晶圓免費 · 見成本恆等式 Zero extra masks ≠ free wafers · see cost identity

法則 #02 · 耐熱嚴格性RULE #02 · THERMAL RIGOR

175°C 結溫等級175°C Tj CLASS

高溫留存等級目標 HIGH-TEMP RETENTION CLASS

架構等級 · 非認證保證 Architecture class · not a cert claim

法則 #03 · 微縮前沿RULE #03 · SCALING EDGE

源自 1.8V CoreFROM 1.8 V CORE

Core 閘氧 AntiFuse 製程窗 CORE-OXIDE ANTIFUSE WINDOW

較厚的 2.5 V 閘氧常先碰上接面崩潰 Thicker 2.5 V oxide often loses to junction BV

法則 #04 · 微縮斷崖RULE #04 · SCALING CLIFF

28nm 停止點28nm STOP GAP

eFlash 浮閘物理斷崖 eFLASH PUMP CHARGE CLIFF

>10V 擦除電壓崩潰 · 無法導入立體鰭片 >10V Erase Collapse · Incompatible with Fins

01 · 全方位技術橫向基準01 · COMPREHENSIVE BENCHMARK

st-nvm-family-v0 · 十一技術九維度對比矩陣 st-nvm-family-v0 · 9-Dimension Benchmark Across 11 Leaf Technologies

評估維度DIMENSION 評估維度Dimension

晶圓製程Foundry eFuse

晶圓製程Foundry Mask ROM

晶圓製程Foundry EEPROM

邏輯 OTPLogic OTP FG-OTP

邏輯 OTPLogic OTP AntiFuse

邏輯 MTPLogic MTP LD-MTP

邏輯 MTPLogic MTP HD-MTP

嵌入式 FlasheFlash SST

嵌入式 FlasheFlash SONOS

新興記憶體Emerging ReRAM

新興記憶體Emerging MRAM

光罩增加道數Mask Adders 晶圓成本加價Wafer cost adder

+0代工標準整合Foundry standard

0–1via／contact 圖樣Via / contact pattern

待查驗VERIFY額外 poly／模組層數Extra poly / module count

+0logic-IP 級Logic-IP class

通常 +0Typically +0通常 +0；供應商分流Typically +0; vendor-split

+0 ~ +2供應商分流；見註腳Vendor-split; see footnote

+4 / 待查驗VERIFY / +10ESF1／ESF2／ESF3ESF1 / ESF2 / ESF3

+2 ~ +4G1 +2–3／G2 +4G1 +2–3 / G2 +4

+2 ~ +4BEOLBEOL

+3 ~ +5BEOL MTJBEOL MTJ

位元胞面積等級Cell Area Class 矽面積量級Silicon footprint class

大Large吹斷級 60–120 F²；I-fuse 熔絲面積另核對Blow-class 60–120 F²; I-fuse fuse area separately

最小Smallest< 8 F²

中Medium20–40 F²

緊湊Compact12–30 F²

極緊湊Ultra-compact10–25 F²

大Large60–120+ F²

中／緊湊Medium/Compact25–50 F²

緊湊Compact12–30 F²

中Medium15–35 F²

緊湊Compact15–35 F²

中Medium30–50 F²

PGM／ERS 機制PGM / ERS Mechanism 寫入與抹除物理Program & erase physics

電遷移熔斷EM link blow吹斷級；I-fuse 另列；CFX 另列 eFuse 商品線Blow class; I-fuse separate; CFX also lists an eFuse SKU

光罩圖樣Mask pattern無電氣 PGMNo electrical PGM

FN / FN雙層多晶矽浮閘Double-poly floating gate

CHEI / None浮閘注入；CFX 亦列此路徑FG inject; CFX also lists this path

閘氧擊穿Gate-oxide breakdown不可逆導通；CFX 教學為閘氧，ZA 位點未公開Irreversible conduction; CFX teaching GOX, ZA site unpublished

FN / FNNeoEE／ZT 級；Actt 未公開NeoEE / ZT class; Actt unpublished

CHI/FN 或 FN/FNCHI/FN or FN/FNNeoMTP 等 CHI/FN；AEON 級 FN/FN — 非 TwinBit SchottkyNeoMTP-class CHI/FN; AEON-class FN/FN — not TwinBit Schottky

SSI / FNSuperFlash SSI／尖端 FNSuperFlash SSI / tip FN

FN / FNG1 捕捉；G2 夾心開關G1 trap; G2 sandwiched switches

Forming + SET/RESET細絲形成與切換Filament form & switch

STT toggle自旋轉矩切換Spin-torque switching

編程電壓與電流Program V / I 隨製程裝置，不是常數Process-set, not a constant

高電流High I吹斷 ~10–15 mA；I-fuse 另列Blow ~10–15 mA; I-fuse separate

不適用N/A光罩寫入Mask write

FN / HV pump~8–14 V 量級~8–14 V class

I/O 裝置視窗I/O device window見註腳 FG-OTPSee FG-OTP footnote

隨 core 閘氧Tracks core oxide數倍 core VddSeveral × core Vdd

FN 視窗FN window低擾動幫浦Low-disturb pump

FN + FN（或 CHI/FN）FN + FN (or CHI/FN)AEON 級 FN 寫抹；NeoMTP 等 CHI/FN — 分流AEON-class FN PGM/ERS; NeoMTP-class CHI/FN — split

SSI + HV pump寫 10V+5V／抹 12–15VProg 10V+5V / Ers 12–15V

FN / HV pumpG1／G2 皆 FN／HV；VDD 是讀G1/G2 both FN/HV; VDD is read

Forming / SETForming 2.5V / SET 1.5VForming 2.5V / SET 1.5V

接近 VDDNear VDD~1.1V · Ic ~30–80 µA~1.1V · Ic ~30–80 µA

高溫留存等級Retention Class 架構等級，非認證Architecture class, not cert

中溫級Mid-temp class吹斷級 ~10 yr @ 125°C；I-fuse 另核對具名 IPBlow-class ~10 yr @ 125°C; I-fuse check named IP

永久級Permanent class光罩固定Mask-fixed

中溫級Mid-temp class~10 yr @ 125°C 量級~10 yr @ 125°C class

高溫級High-temp class~10 yr @ 175°C（架構級，非認證；Synopsys public）量級~10 yr @ 175°C (architecture class, not cert; Synopsys public)

中溫級Mid-temp class~10 yr @ 125°C 量級~10 yr @ 125°C class

高溫車規級Auto Grade 010 yr @ 150°C / 20 yr @ 125°C10 yr @ 150°C / 20 yr @ 125°C

具名分流Named splitG1 中溫級；G2 表列 175°CG1 mid-temp; G2 table 175°C

商業/工業級Commercial/Ind~10 yr @ 85–105°C~10 yr @ 85–105°C

中溫級Mid-temp class~10 yr @ 125°C 量級~10 yr @ 125°C class

讀取延遲（陣列／SA）Read Latency (Array / SA) 非 SRAM shadow 路徑Not SRAM shadow path

~1 µs開機 shadow 到 SRAMBoot-shadow to SRAM

~5–15 ns靜態 1T 陣列Static 1T array

~20–40 nsSA 翻轉受限SA trip limited

~25–40 nsSA 翻轉受限SA trip limited

~25–40 ns受 cell current 限制Cell-current limited

~20–40 nsSA 翻轉受限SA trip limited

~15–25 ns分離閘極較快Split-gate faster

~20–35 nsG1 2T；G2 VDD 讀仍為陣列／SAG1 2T; G2 VDD-read still array/SA

數十 nsTens of ns陣列／SA 受限Array / SA limited

~10–25 nsTMR 裕度與防擾動限制TMR margin & disturb bound

覆寫耐久度Endurance 可重寫次數等級Rewrite cycle class

1 次1 cycle不可逆Irreversible

10⁴–10⁵氧化層磨耗Oxide wear

1 次1 cycleOTP 單調OTP monotonic

1 次1 cycle不可逆Irreversible

10⁴–10⁵家族量級；ZT 本文／表衝突，非保證Family class; ZT body/table conflict, not a guarantee

10³–10⁴FN 穿隧／介面磨耗（AEON 級）；CHI 路線另計FN tunneling / interface wear (AEON-class); CHI routes differ

10⁴–10⁵氧化層磨耗Oxide wear

10⁴–10⁵捕捉層磨耗；G2 開發中，非量產保證Trap-layer wear; G2 in development, not a production guarantee

10⁵–10⁶細絲磨耗Filament wear

10⁶–10¹⁰受限於 ~1nm MgO TDDB（例：GF IRPS 2019）Bounded by MgO TDDB (e.g. GF IRPS 2019)

製程微縮Scaling 成熟下限與先進上限Mature floor & advanced ceiling

電流／IR 受限Current / IR limited吹斷級；I-fuse 另列Blow class; I-fuse separate

金屬間距Metal pitch接觸密度受限Contact density bound

平面 ~90/130 nmPlanar ~90/130 nm雙層多晶矽熱預算限制DP thermal budget bound

I/O 或 logic FGI/O or logic FG依整合路徑Integration-path set

微縮至 2nm GAA（vendor/gen；例：VLSI 2025 DOI）Down to 2nm GAA (vendor/gen; e.g. VLSI 2025 DOI)GAA 類常被定位為 0-Mask OTP（依世代／供應商）Often positioned as 0-mask OTP in GAA class (vendor/generation dependent)

平面 ~28 nm 止點Planar ~28 nm limit單層浮閘；TwinBit 不屬此葉Single-poly FG; TwinBit not this leaf

平面 ~28 nmPlanar ~28 nmHV 幫浦 vs FinFETHV pump vs FinFET

平面 ~28 nmPlanar ~28 nmG1 公開至 40 nm；G2 55BCDG1 public to 40 nm; G2 55BCD

BEOLForming 隨節點Forming node-set

BEOL MTJ隨代工 BEOLFoundry BEOL set

防竄改幾何Anti-Tamper Geometry TEM／探針衰減，非免疫TEM / probe attenuation, not immunity

熔斷空洞可見Melt void visible吹斷級 SEM；I-fuse 另列Blow-class SEM; I-fuse separate

去層全暴露De-layer exposed光學可見Optically visible

電荷探測Charge probingEM／雷射攻擊面EM / laser attack surface

浮閘電荷FG charge電荷／雷射面Charge / laser surface

次閘氧微絲Sub-gate filamentFIB 衰減，非免疫FIB attenuation, not immunity

浮閘電荷FG charge電荷探測面Charge probe surface

捕捉層電荷Trap charge電荷探測面Charge probe surface

細絲部分可見Filament partly visibleSTEM 可觀測STEM observable

磁化可探Magnetization probeableMFM 攻擊面MFM attack surface

工程註解與邊界NOTES & BOUNDARIES 架構工程邊界與九維度註解規範 Architectural Boundary & 9-Dimension Engineering Notes

⚠️ 表內數據為架構量級，非具名巨集 Datasheet 或出貨保證；零額外光罩 ≠ 晶圓免費 ⚠️ Figures are architecture-class ranges, not named-macro datasheets; zero extra masks ≠ free wafers

01 · 光罩加價與晶圓經濟學01 · MASK ADDERS & WAFER ECONOMICS

光罩加價道數與供應商分流 Mask Adders & Vendor Split

光罩增加道數為架構等級：Architecture Class: 非代工廠 PDK 報價。EEPROM-DP 不得硬編 +4–8，再計額外 poly／模組層數。 Not PDK quotes. Do not hard-code EEPROM-DP at +4–8; count extra poly/module layers.
MTP 供應商分流：MTP Vendor Split: LD-MTP 通常為 +0（如 NeoEE、Floadia LEE Flash ZT）。HD-MTP 須分流：Impinj／AEON 級 +0；YMC +0–2；eMemory NeoMTP baseline +0、gen2 +2（well-implant 光罩，單元面積 25–50 F²，見 ChipEstimate 2022-11-29）。Actt LogicFlash® 公開為 180–55 nm、+0–1，機制未公開，不得回填 FN/FN 或 CHI/FN。NSCore TwinBit™ Gen-2 為 0 光罩 Pch Schottky，不得併入 LD／HD 浮閘葉。 LD-MTP is typically +0 (e.g. NeoEE, Floadia LEE Flash ZT). HD-MTP requires vendor split: Impinj/AEON +0; YMC +0–2; eMemory NeoMTP baseline +0 / gen2 +2 (well-implant masks, cell 25–50 F² per ChipEstimate 2022-11-29). Actt LogicFlash® is public at 180–55 nm, +0–1, with unpublished cell physics — do not back-fill FN/FN or CHI/FN. NSCore TwinBit™ Gen-2 is 0-mask Pch Schottky and must not be merged into the LD/HD floating-gate leaves.
eFlash 模組階梯：eFlash Hierarchy: SST 不得合併：ESF1 例 +4（GF 130BCDLite）；ESF2 VERIFY；ESF3 例 +10（GF 28SLPe 含 5V I/O）。SONOS 須分流：Floadia G1 級 +2–3（180 BCD 公開表列例為 +2），非 +6–10；G2 公開為 +4（55 BCD 表列，開發中），讀取為 VDD、SONOS 夾於開關電晶體之間。原廠 PDK／SPICE 保留（G1／G2 公開頁）。 SST must not be lumped: ESF1 ex. +4 (GF 130BCDLite); ESF2 VERIFY; ESF3 ex. +10 (GF 28SLPe incl. 5V I/O; Microchip/GF public). SONOS requires a named split: Floadia G1-class +2–3 (180 BCD public table lists +2), not +6–10; G2 is public at +4 (55 BCD table, in development) with VDD-read and a SONOS cell sandwiched by switch transistors. Original PDK/SPICE preserved (G1 / G2 public pages).

02 · 單元拓撲與微縮斷崖02 · CELL TOPOLOGY & SCALING CLIFF

位元胞幾何與 3D 微縮邊界 Cell Geometry & 3D Scaling Limits

單元面積物理約束：Cell Area Constraint: LD-MTP 因需 >80% 電容耦合比，單元面積達 60–120+ F²；具名 CHI 路線的 HD-MTP 可藉熱載子注入縮小耦合電容至 25–50 F²（不含 AEON FN/FN 寫抹）。 LD-MTP requires >80% coupling ratio, requiring 60–120+ F² cells; named CHI-route HD-MTP leverages hot-carrier injection to compress cell area to 25–50 F² (excludes AEON FN/FN program).
FinFET 3D 閘極微縮斷崖：FinFET 3D Scaling Cliff: 單層多晶矽浮閘 MTP 受限於平面擴散區耦合電容與 3D 鰭狀閘極幾何衝突，其製程微縮止於 28nm/22nm 平面節點，無法延伸至 FinFET。此斷崖適用 LD-MTP／HD-MTP 浮閘葉，不適用 NSCore TwinBit™ Gen-2：原廠公開為 Pch Schottky 單元、0 額外光罩、40–22 nm 及 beyond（TwinBit Gen-2），不得把 Schottky 熱載子路徑回填成單層浮閘。 Single-poly floating-gate MTP scaling stops at 28nm/22nm planar nodes due to 3D FinFET coupling-capacitor topology barriers. That cliff applies to the LD-MTP / HD-MTP FG leaves, not to NSCore TwinBit™ Gen-2: the vendor page is a Pch Schottky cell, 0 extra masks, 40–22 nm and beyond (TwinBit Gen-2). Do not back-fill Schottky hot-carrier physics onto single-poly FG.
先進節點 0-Mask 延伸：Advanced Node Extension: AntiFuse 編程在教學葉上常是 core 裝置閘氧崩潰：Vpgm 由該製程閘氧厚度與允許擊穿時間決定；常被定位為可隨 core 縮放進入含 2nm GAA 的先進節點類別（依 vendor／世代；公開矽例 VLSI 2025 DOI，非萬能保證）。CFX 教學預設才是閘氧路徑。Floadia LEE Fuse ZA 可掛同一葉，但公開只到介電層永久導通，不指定擊穿點在閘極或電容，不得把閘氧微絲模型套上去；涵蓋 180 nm 至 sub-10 nm，量產軌跡為 1x nm DRAM，28 nm 邏輯列為開發中（LEE Fuse ZA）。 On the teaching leaf, AntiFuse programming is often core-device gate-oxide breakdown, with Vpgm set by that process oxide and allowed time-to-breakdown; it is often positioned to scale into advanced GAA classes including 2nm (vendor/generation dependent; public Si ex. VLSI 2025 DOI — not a universal guarantee). The CFX teaching default is the GOX path. Floadia LEE Fuse ZA may sit on the same leaf, but it is published only as a dielectric made permanently conductive and does not locate the breakdown in a gate or a capacitor — do not apply the GOX filament model. Public coverage is 180 nm to sub-10 nm, with a 1x nm DRAM mass-production track and 28 nm logic listed as under development (LEE Fuse ZA).

03 · 寫入機制與可靠度邊界03 · PROGRAMMING & RELIABILITY

載子傳輸機制與耐久度極限 Carrier Transport & Endurance Limits

SST 來源端注入 (SSI)：SST Source-Side Injection: SST 寫入採用專利來源端注入（SSI）高效率熱電子傳輸，抹除則為多晶矽尖端 FN 穿隧（SST SuperFlash 公開族）。NSCore TwinBit™ Gen-2 寫入為熱電洞、抹除為熱電子（Pch Schottky；原廠 TCAD 頁），不得與 SSI、FN/FN 或 CHI/FN 互換。Attopsemi I-fuse® 為熱輔助電遷移、刻意低於熱失控吹斷（I-fuse；IEEE JEDS 2019 22 nm FD-SOI 例約 1 V／1 mA），不得與代工標準 eFuse 熔斷、閘氧 AntiFuse 或浮閘 OTP 合併。 SST programming relies on patented Source-Side Injection (SSI) and poly-tip FN erase (SST SuperFlash family). NSCore TwinBit™ Gen-2 programs by hot holes and erases by hot electrons (Pch Schottky; vendor TCAD page) and must not be swapped with SSI, FN/FN, or CHI/FN. Attopsemi I-fuse® is heat-assisted electromigration deliberately below thermal-runaway blow (I-fuse; IEEE JEDS 2019 22 nm FD-SOI example ~1 V / ~1 mA) and must not be merged with foundry-standard eFuse blow, gate-oxide AntiFuse, or floating-gate OTP.
eMRAM TDDB 壽命極限：eMRAM TDDB Limit: 代工量產 eMRAM 覆寫常以約 1 nm MgO 穿隧絕緣層 TDDB 為架構級邊界（公開例 GF IRPS 2019，仍須對照目標 vendor 表）：eFlash 替換模式常見量級 10⁵–10⁶ 次，工作快取模式 10⁸–10¹⁰ 次，不應與實驗室原型之 >10¹² 次混淆。 Commercial eMRAM endurance is commonly framed by ~1nm MgO TDDB as an architecture-class bound (e.g. public ex. GF IRPS 2019; still confirm target vendor tables): often 10⁵–10⁶ for eFlash-replacement class and 10⁸–10¹⁰ for cache class, distinct from >10¹² lab prototypes.
STT-MRAM 陣列讀取延遲：STT-MRAM Read Latency: 受限於 100%–180% 之微弱 TMR 信號與防止誤翻轉之低壓偏置，原生陣列延遲為 10–25 ns，非 SRAM 級別之 1–2 ns。 STT-MRAM array read latency is 10–25 ns due to 100%–180% TMR margins and disturb bounds, not 1–2 ns SRAM-speed.

04 · 電壓視窗與實體安全04 · VOLTAGE WINDOWS & SECURITY

電壓視窗與實體安全責任鏈 Voltage Windows & Layered Security

編程電壓視窗區隔：Voltage Window Separation: 公開專利把約 32 Å 閘氧的 VPP 放在 8–9 V、約 20 Å 放在 5–6 V；原廠具名製程例顯示 1.8 V core 須承受遠高於 Vdd 的編程應力。FG-OTP 的 I/O 浮閘熱載子注入（3.3 V／5 V PMOS 約 6.5 V／7.5 V PGM）為公開文獻／架構量級，不得回填到 core 閘氧 AntiFuse。 Public teaching places VPP near 8–9 V for ~32 Å and 5–6 V for ~20 Å. FG-OTP I/O floating-gate HCI (~6.5 V on 3.3V PMOS, ~7.5 V on 5V) is public literature and must not be back-filled onto core-oxide AntiFuse.
讀取延遲與開機快取：Read Path & Boot Shadowing: 讀取延遲指陣列／sense amplifier 路徑；吹斷級 eFuse 原生約 µs 量級，實務上開機 shadow 到 SRAM。OTP 陣列讀取普遍極限約 25 ns、多數約 40 ns。SST 分離閘極 eFlash 通常稍快，約 15–25 ns 量級。I-fuse 讀熔絲電阻；閘氧 AntiFuse 讀閘極電流；ZA 感測路徑未公開。延遲仍以該版巨集為準，不得把 µs 原生 eFuse 數字套到 I-fuse。 Read latency is array/SA path. Native blow-class eFuse sensing is ~µs-class, shadowed to SRAM at boot. OTP array reads typically sit near 40 ns, practical floor ~25 ns. SST split-gate is ~15–25 ns class. I-fuse reads fuse resistance; GOX AntiFuse reads gate current; ZA sense path is unpublished. Keep native µs eFuse figures off I-fuse macros.
TEM / DPA 防護責任鏈：TEM / DPA Layered Defense: 非揮發微絲為永久性物理歐姆結構，位元單元本身無法「單週期自我清除」；系統防護依賴主動頂層金屬網感測觸發揮發暫存器即時清零。TEM／DPA 描述為幾何與架構衰減，非絕對免疫。具名產品仍以該版 IP 為準。 Physical filament is an irreversible ohmic structure and cannot self-zeroize; system defense relies on active mesh detecting tampering to zeroize volatile shadow registers. TEM/DPA descriptions represent geometric/architectural attenuation, not absolute immunity. Check the specific IP revision.

05 · 具名 IP 歸屬與查核05 · NAMED IP UNDER FAMILY LEAVES

具名 IP 對應既有 11 葉（機制不同者不併欄） Named IPs Map onto the 11 Leaves (Do Not Merge Distinct Physics)

OTP
CFX 公開三條路徑——閘氧 AntiFuse、eFuse、浮閘 OTP——教學預設為閘氧崩潰，不得把三條路徑併成同一格（單元導讀；chuangfeixin.com）。Floadia LEE Fuse ZA 掛 AntiFuse 葉：0 額外光罩、180 nm 至 sub-10 nm；公開只到介電層永久導通，擊穿位點未指定，不得寫成閘氧路徑；頁面曾寫「LEE Flash ZA」，產品名仍為 LEE Fuse ZA（單元導讀）。Attopsemi I-fuse® 掛 eFuse 族群但不是吹斷級 eFuse、也不是 AntiFuse：poly／metal-gate／metal fuse，熱輔助電遷移且低於熱失控（單元導讀）。 CFX publishes three routes — GOX AntiFuse, eFuse, and floating-gate OTP — the teaching default is oxide breakdown and the three must not collapse into one cell (cell study; chuangfeixin.com). Floadia LEE Fuse ZA sits on the AntiFuse leaf: 0 extra masks, 180 nm to sub-10 nm; published only as a dielectric made permanently conductive, breakdown site unpublished — not a GOX path; the page once says “LEE Flash ZA”, but the product name is LEE Fuse ZA (cell study). Attopsemi I-fuse® sits in the eFuse family but is not blow-class eFuse and not AntiFuse: poly / metal-gate / metal fuse programmed by heat-assisted EM below thermal runaway (cell study).
MTP
Floadia LEE Flash ZT 掛 LD-MTP 葉：0 光罩、FN 寫／抹、浮閘（新聞稿）；公開頁 P/E 次數本文與表不一致，不得當共通保證（單元導讀）。Actt LogicFlash® MTP（CMT 為 2016 年收購沿革，不是現行 SKU）公開 180–55 nm、+0–1、類 Flash 的 byte PGM／sector 或 chip ERS；產品頁最高約 10k 次，非本表保證；單元物理未公開（單元導讀）。NSCore TwinBit™ Gen-2 不掛 LD 也不掛 HD：Pch Schottky、熱電洞寫入／熱電子抹除、40–22 nm、0 光罩（單元導讀）。PermSRAM 是 OTP 旁系（熱載子進 SiN 側壁），不得與 TwinBit 合併。 Floadia LEE Flash ZT sits on the LD-MTP leaf: 0 extra masks, FN program/erase, floating gate (press). Public P/E-cycle body vs table conflict — not a common guarantee (cell study). Actt LogicFlash® MTP (CMT is 2016 acquisition lineage, not a current SKU) is public at 180–55 nm, +0–1, Flash-like byte PGM / sector or chip ERS; product-page up to ~10k cycles, not a table guarantee; cell physics unpublished (cell study). NSCore TwinBit™ Gen-2 sits on neither LD nor HD: Pch Schottky, hot-hole program / hot-electron erase, 40–22 nm, 0 extra masks (cell study). PermSRAM is an OTP sibling (hot-carrier into SiN sidewall) and must not merge with TwinBit.
eFlash
SST 葉即 SST SuperFlash 分離閘極族（SSI／interpoly FN；公開節點約 180–28 nm，首頁亦見 500 nm–28 nm）（單元導讀）。Floadia G1 掛 SONOS 葉：+2–3、FN P/E、BCD（單元導讀）。G2 同為 SONOS 但 +4、VDD 讀、夾心開關、55 BCD 表列且標示開發中（單元導讀）；VLSI-DAT 2020 以 TCAD 討論低於 28 nm 的可行性，不是 FinFET 量產聲明。 The SST leaf is the SST SuperFlash split-gate family (SSI / interpoly FN; public foundry nodes ~180–28 nm; home also states 500 nm–28 nm) (cell study). Floadia G1 sits on the SONOS leaf: +2–3, FN P/E, BCD (cell study). G2 is also SONOS but +4, VDD-read, sandwiched switches, 55 BCD table, marked in development (cell study); VLSI-DAT 2020 discusses sub-28 nm feasibility in TCAD — not a FinFET production claim.

02 · 示範性啟發實驗室（非生產選型器）02 · DEMO HEURISTIC LAB (not a production selector)

5 軸多維動態雷達選型演示（相對適配分；非 production selector） 5-Axis Multidimensional Architecture Radar Selector (demo heuristic)

調節五大設計約束滑桿，即時畫出各技術相對輪廓。分數為示範性 heuristic demo（相對適配），不是 production selector、不是預設贏家、也不是出貨證明。輪廓為族群級：eFuse 為吹斷級；I-fuse 與 Logic MTP 另列候選。TwinBit／Actt／G2 等具名例外見矩陣註解 05，不另畫獨立輪廓。 Move the five constraint sliders to redraw relative hulls. Scores are a heuristic demo of relative fit under the current sliders — not a production selector, not a default winner, and not shipment proof. Hulls are family-class: eFuse is blow-class; I-fuse and Logic MTP are listed as separate candidates. Named exceptions (TwinBit / Actt / G2) stay in matrix note 05 and do not get extra hulls.

① 製程微縮節點 (PROCESS NODE) ① PROCESS NODE SCALING 22nm (Planar HKMG)

180nm40nm22nm12nm2nm GAA

② 晶片功耗預算 (POWER BUDGET) ② ACTIVE POWER BUDGET 1.0 mW (IoT / Edge)

0.1mW (ULP)1mW (Edge)25mW (Auto)250mW (HPC)

③ 額外光罩預算 (MASK ADDER) ③ MASK ADDER OVERHEAD 0-Mask (Pure Logic)

0-Mask (logic)3~5 Adders (BEOL)8~12 Adders (eFlash)

④ 耐溫與可靠度 (TEMP GRADE) ④ TEMPERATURE GRADE 175°C Tj target (not blanket G0 cert)

85°C (Commercial)125°C (Grade 1)175°C Tj (design target)

⑤ 寫入次數需求 (REWRITE CYCLES) ⑤ REWRITE ENDURANCE 1~100 (RoT / Patching)

1~100 (OTP/Patch)10K~100K (MTP/OTA)>1M (Working RAM)

5 軸架構取捨雷達 5-AXIS ARCHITECTURAL TRADE-OFF RADAR

● AntiFuse OTP（相對適配）AntiFuse OTP (relative fit) ● STT-eMRAM（次適配）STT-eMRAM (next)

［相對適配］[RELATIVE FIT]

相對適配計算中… Computing relative fit…

03 · 第一性原理物理模型03 · FIRST-PRINCIPLES MODELS

第一性原理物理模型與晶圓成本經濟學方程式 First-Principles Physics & Wafer Economics Equations

三條可推導檢驗的第一性原理恆等式：穿隧與微絲擊穿、光罩階梯加價與良率、次閾值擴散漏電。用來嚴格約束架構選型，而非代工廠報價或單次宣稱。 Three inspectable first-principles identities — tunneling & filament breakdown, mask-adder & yield economics, subthreshold diffusion leakage — constrain architectural selection.

公式 01 · 反熔絲穿隧與擊穿EQUATION 01 · ANTIFUSE BREAKDOWN

Fowler–Nordheim 穿隧與局域矽微絲擊穿 Fowler–Nordheim Tunneling & Localized Filament Breakdown

穿隧機制由能障形狀主導：超薄氧化層在 t_ox ≤ 3.0 nm 且 V_ox < Φ_B/q (~3.15 V) 時為梯形能障直接穿隧 (Direct Tunneling)；當 V_ox > Φ_B/q 時轉為三角形能障 Fowler–Nordheim (FN) 穿隧，有效穿隧距離縮短為 x_t = Φ_B/(qE_ox)。強電場 E_ox ≥ 6~10 MV/cm 下缺陷累積觸發滲透熱失控，形成不可逆的再結晶矽導電微絲： Regime governed by barrier shape: ultrathin oxide at t_ox ≤ 3.0 nm and V_ox < Φ_B/q (~3.15 V) exhibits trapezoidal direct tunneling; V_ox > Φ_B/q triggers triangular FN tunneling with tunneling distance x_t = Φ_B/(qE_ox). High field E_ox ≥ 6~10 MV/cm drives defect percolation and thermal runaway into a permanent recrystallized silicon filament:

J_FN = A_FN · E_ox² · exp(−B_FN / E_ox)

• 穿隧係數理論解：A_FN = q²(m₀/m*) / (8π h Φ_B) ≈ 1.2×10⁻⁶ A/V²；B_FN = 4√(2m*q) Φ_B^3/2 / (3ℏ) = 8π√(2m*q) Φ_B^3/2 / (3h)。
• 常數基準校正：Si–SiO₂ 能階差 Φ_B ≈ 3.15 eV。若取自由電子有效質量 m* ≈ 0.50 m₀，理論值 B_FN ≈ 2.70×10⁸ V/cm (270 MV/cm)；若採 Lenzlinger–Snow 實驗穿隧質量 m* ≈ 0.42 m₀（含影像力修正），則 B_FN ≈ 2.48×10⁸ V/cm ≈ 2.5×10⁸ V/cm。
• 微觀崩潰四階段：高場應力誘發氧空位與 E' 中心缺陷生成 → 達滲透閾值 (N_bd ≈ 10¹⁹~10²⁰ cm⁻³) 觸發軟崩潰 (SBD) → 焦耳熱集中引發熱失控硬崩潰 (HBD, 局部 T > 1400°C) → 矽原子遷移凝固為直徑 5~10 nm 的局域再結晶矽微絲，阻抗由 >10¹¹ Ω 驟降至 10² Ω 歐姆態。此為不可逆之金屬/半導體相變，非 ReRAM 可逆微絲。
• 編程電壓縮放：V_prog 由 E_ox × t_ox 及擊穿時間 t_bd 約束，隨 Core 閘氧厚度按比例縮放（如 28nm ~ 1.8V-2.5V），不可將 5V/3.3V I/O 浮閘 HCI 的 6.5V~7.5V 數值回填混淆。
• 適用範圍：此式描述 core 閘氧 AntiFuse（含 CFX 教學路徑）。Floadia LEE Fuse ZA 只公開介電層永久導通，擊穿位點未指定，不得套用本微絲模型。 • Theoretical Coefficients: A_FN = q²(m₀/m*) / (8π h Φ_B) ≈ 1.2×10⁻⁶ A/V²; B_FN = 4√(2m*q) Φ_B^3/2 / (3ℏ) = 8π√(2m*q) Φ_B^3/2 / (3h).
• Constant Calibration: Barrier Φ_B ≈ 3.15 eV. Theoretical B_FN ≈ 2.70×10⁸ V/cm (270 MV/cm) with m* ≈ 0.50 m₀; empirical Lenzlinger–Snow value gives B_FN ≈ 2.48×10⁸ V/cm ≈ 2.5×10⁸ V/cm with m* ≈ 0.42 m₀.
• 4-Stage Breakdown Physics: Stress defect generation → Percolation threshold (N_bd ≈ 10¹⁹~10²⁰ cm⁻³) soft breakdown (SBD) → Joule heating thermal runaway hard breakdown (HBD, T > 1400°C) → Molten silicon migration forming 5~10 nm recrystallized silicon filament shifting resistance from >10¹¹ Ω to 10² Ω ohmic state. Permanent metallurgical phase change, unlike ReRAM.
• Scaling Constraint: V_prog scales with Core E_ox × t_ox and allowed t_bd; never back-fill 6.5V~7.5V I/O floating-gate HCI voltages onto thin-oxide AntiFuse.
• Scope: this identity describes core-GOX AntiFuse, including the CFX teaching route. Floadia LEE Fuse ZA is published only as a dielectric made permanently conductive; the breakdown site is unpublished — do not apply this filament model to ZA.

公式 02 · 晶圓成本與良率EQUATION 02 · WAFER COST & YIELD

額外光罩晶圓成本與良率恆等式 Mask-Adder Wafer Cost & Effective Yield Identity

將額外光罩道數 ΔN_mask、前段/後段邊際加價 α_mask 與製程良率衝擊 ΔY 結合成可物理檢查的成本閉環： Integrate extra masks ΔN_mask, FEOL/BEOL marginal adders α_mask, and process yield hits ΔY into an inspectable cost closure:

C_die,eff = [C_base · (1 + Σ α_i)] / [GDPW(A_die) · (Y_base − ΔY_nvm)]

• 光罩邊際成本差異 (α_mask)：FEOL 關鍵層涉及高能植入與高溫退火，邊際加價率 α_FEOL ≈ 2.5%~4.0%/mask；BEOL 金屬穿插層邊際加價率 α_BEOL ≈ 1.5%~2.5%/mask。
• 技術陣營量級：
  – SST-class eFlash：FEOL ΔN_mask 常為 +4（ESF1 例）至 +10（ESF3 例），不得把所有 eFlash 硬編 8~12。
  – SONOS eFlash：Floadia G1 公開 +2~3；G2 公開 +4（55 BCD，開發中）。
  – STT-MRAM：BEOL ΔN_mask = 3~5，晶圓加價 ΔC_wafer ≈ +15%~22%，金屬回濺增加缺陷密度 ΔD₀。
  – 0-mask 邏輯 NVM：AntiFuse、吹斷級 eFuse、I-fuse、LD-MTP（NeoEE／ZT）、TwinBit 均為 ΔN_mask = 0；單元統計與感測面積仍佔矽。零額外光罩 ≠ 晶圓免費。 • Marginal Mask Adders (α_mask): FEOL critical layers involve high-energy implants and thermal cycles (α_FEOL ≈ 2.5%~4.0%/mask); BEOL interconnect modules add α_BEOL ≈ 1.5%~2.5%/mask.
• Technology Spectrum:
  – SST-class eFlash: FEOL ΔN_mask commonly +4 (ESF1 class) to +10 (ESF3 class); do not hard-code every eFlash at 8~12.
  – SONOS eFlash: Floadia G1 public +2~3; G2 public +4 (55 BCD, in development).
  – STT-MRAM: BEOL ΔN_mask = 3~5, wafer adder ΔC_wafer ≈ +15%~22%, physical sputter redeposition alters defectivity ΔD₀.
  – 0-mask logic NVM: AntiFuse, blow-class eFuse, I-fuse, LD-MTP (NeoEE / ZT), and TwinBit are ΔN_mask = 0; cell statistics and sense area still occupy silicon. Zero extra masks ≠ free wafers.

公式 03 · 次閾值擴散漏電EQUATION 03 · SUBTHRESHOLD DIFFUSION

次閾值擴散漏電與玻爾茲曼極限 Subthreshold Diffusion Leakage & Boltzmann Tyranny

超低功耗邊緣節點 Always-On 域，關態靜態漏電由次閾值擴散機制與源汲熱平衡因子共同決定： Static leakage in always-on edge MCU domains is dominated by subthreshold diffusion and the drain balance factor:

I_sub = μ_eff C_ox (W/L) (k_BT/q)² (m−1) · exp[(q(V_gs−V_th))/(m k_BT)] · [1 − exp(−q V_ds / k_BT)]

• 亞閾值擺幅 (S) 與熱力學極限：S = ln(10) · m · (k_BT/q) ≈ 59.5 · m mV/dec (@ 300 K)。在理想閘極靜電控制下 (m → 1.0)，受限於玻爾茲曼統計極限 60 mV/dec；平面 CMOS 因空乏層分壓 m = 1 + C_dep/C_ox ≈ 1.2~1.4，實測 S ≈ 70~85 mV/dec。
• 汲極飽和抑制因子：[1 − exp(−qV_ds/k_BT)] 在 V_ds ≥ 3 k_BT/q (~78 mV) 時迅速飽和趨近於 1；在 V_ds → 0 時線性歸零，嚴格滿足熱力學平衡零流約束。
• 長效待機啟示：感測路徑若採用 Power-Gating 或深次閾值偏置，靜態漏電可壓制在 <10 nA 等級，惟需經晶圓製程角 (Corner) 與高溫 (125°C) 矽驗證。 • Subthreshold Swing (S) & Boltzmann Limit: S = ln(10) · m · (k_BT/q) ≈ 59.5 · m mV/dec (@ 300 K). Under ideal electrostatic coupling (m → 1.0), constrained by the 60 mV/dec thermal limit; planar CMOS exhibits m = 1 + C_dep/C_ox ≈ 1.2~1.4, yielding S ≈ 70~85 mV/dec.
• Drain Saturation Factor: [1 − exp(−qV_ds/k_BT)] saturates to ~1 when V_ds ≥ 3 k_BT/q (~78 mV) and vanishes linearly at zero bias, satisfying thermodynamic equilibrium.
• Standby Implication: Gated sense paths suppress standby drain to <10 nA class, subject to silicon corner and high-temperature (125°C) validation.

04 · 晶圓代工與實體安全04 · FOUNDRY & SECURITY

主流晶圓代工與專用類比製程路線圖暨實體防護機制 Foundry & Specialty Analog Ecosystem Roadmap & Physical Security Integrity

主流晶圓代工廠真實 PDK 量產狀態、車規等級驗證進展與奈米級實體防護責任鏈。 Foundry PDK qualification envelopes, automotive grade readiness, and layered physical anti-tamper security chains.

晶圓廠 01 · 台灣積體電路 (TSMC)FOUNDRY 01 · TAIWAN SEMICONDUCTOR

TSMC

40nm / 28nm eFlash & 28eHV 0-mask OTP 須分流機制0-mask OTP: split mechanisms 微縮斷崖Scaling Cliff

40LP/ULP 與 28HPC+ 為車用 eFlash 長期主力，但 28nm 面臨 SST 級 8~12 道額外光罩與 >1000°C 熱預算破壞 HKMG 之微縮斷崖；SONOS G1／G2 光罩階梯較低，須逐家 PDK 核對。28eHV 普遍以 0-mask AntiFuse OTP 進行 OLED Gamma/De-Mura 校準；同節點仍須分流未公開擊穿位點的 ZA 類與 I-fuse，不得預設單一機制。 40LP/ULP & 28HPC+ are mature eFlash bastions; scaling beyond 28nm hits an SST-class 8-12 mask adder cliff and HKMG thermal destruction. SONOS G1/G2 sit on a lower mask ladder and must be checked per PDK. 28eHV adopts 0-mask AntiFuse OTP for OLED Gamma/De-Mura trimming; still split unpublished-site ZA-class and I-fuse — do not assume one mechanism.

22ULL / 22ULP 0-mask OTP 須分流機制0-mask OTP: split mechanisms 車規 Grade 1Auto Grade 1

eRRAM 於 2022 年量產並於 2025 年通過 AEC-Q100 Grade 1 (10萬次循環)；STT-eMRAM 商業量產；純邏輯 0-mask OTP 作為標配時須分流閘氧 AntiFuse、擊穿位點未公開的 ZA 類、以及 I-fuse，不得預設單一機制。 eRRAM entered production in 2022, qualifying for AEC-Q100 Grade 1 (100K cycles) in 2025; STT-eMRAM production-ready; logic 0-mask OTP as a standard option still requires a gate-oxide AntiFuse vs unpublished-site ZA-class vs I-fuse split rather than a single assumed mechanism.

16FFC / 12FFC+ (N12e) 100萬次 <1 ppm<1 ppm @ 1M

16FFC eMRAM 於 2023 年通過 Grade 1，第二代 16MRAM 於 2025 年達成 100 萬次循環失效率 <1 ppm；N12e eRRAM 於 2025 年完成生產級消費資格。 16FFC eMRAM passed Grade 1 in 2023; Gen-2 16MRAM qualified in 2025 with <1 ppm failure rate at 1M cycles; N12e eRRAM production consumer qualification in 2025.

N6e / N4e / N2 GAA 0-mask OTP 須分流機制0-mask OTP: split mechanisms 奈米片信任根Nanosheet RoT

N6e (6nm) eRRAM 與 N4e/N5 5nm 高速 eMRAM 開發中；N2 奈米片因 BEOL 熱預算與微縮限制，公開敘事常以純邏輯 0-mask OTP 作為硬體信任根，但仍須分流閘氧 AntiFuse、擊穿位點未公開的 ZA 類、以及 I-fuse，不得預設單一機制。 N6e 6nm eRRAM and N4e/N5 5nm high-speed eMRAM in R&D; N2 GAA nanosheet public narratives often use 0-mask logic OTP as the Root of Trust due to BEOL thermal constraints, but still require an AntiFuse vs unpublished-site ZA vs I-fuse split rather than one assumed mechanism.

晶圓廠 02 · 聯華電子 (UMC)FOUNDRY 02 · UNITED MICROELECTRONICS

UMC

55nm / 40nm eFlash & 40/28eHV 0-mask OTP 須分流機制0-mask OTP: split mechanisms 量產 SSIProduction SSI

採用 SST SuperFlash 分離閘極技術量產車用 Grade 1 eFlash；40/28eHV 驅動 IC 整合高壓校準 OTP。同節點校準 OTP 仍須分流閘氧 AntiFuse、擊穿位點未公開的 ZA 類、以及 I-fuse，不得預設單一機制。 Production SST SuperFlash split-gate for Auto Grade 1 MCUs; 40/28eHV DDICs incorporate trim OTP. Same-node trim OTP still requires a gate-oxide AntiFuse vs unpublished-site ZA-class vs I-fuse split — do not assume one mechanism.

28HPC+ / 22ULL (MRAM & RRAM) 商用 P-SRAMCommercial P-SRAM

與 Avalanche 合作之 22nm pMTJ STT-MRAM 於 2022 年商業量產 (P-SRAM)；22ULL eMemory RRAM IP 於 2023 認證，智原 FlashKit-22RRAM 平台於 2025 完成流片驗證。 Avalanche 22nm pMTJ STT-MRAM in commercial production since 2022 (P-SRAM); 22ULL eMemory RRAM IP qualified in 2023; Faraday FlashKit-22RRAM SoC tape-out validated in 2025.

邏輯 OTP / MTP 生態系Logic OTP / MTP Ecosystem 原生 0 光罩0-Mask Native

公開 PDK 常見力旺 (NeoBit / NeoFuse) 與晶豪科旗下 YMC (yMTP BBHH) 0-mask 組合；NSCore TwinBit、Floadia ZA／ZT、Attopsemi I-fuse 等其他 0-mask IP 須逐家核對 PDK，不得由本句推論「已全面支援」。 Public PDK coverage commonly includes eMemory (NeoBit/NeoFuse) and YMC (yMTP BBHH) 0-mask logic NVM across 55nm–22nm. Other 0-mask IPs (NSCore TwinBit, Floadia ZA/ZT, Attopsemi I-fuse) must be checked per foundry PDK — this sentence does not imply blanket support.

晶圓廠 03 · 格羅方德 (GLOBALFOUNDRIES)FOUNDRY 03 · GLOBALFOUNDRIES

GlobalFoundries

22FDX / FDX+ (FD-SOI) 車規 150°C 就緒AutoPro150 Ready

2020 年業界首創生產就緒 eMRAM；2026 年 FDX+ AutoPro150 達成 Grade 1 ready (150°C、50萬次、<10ns讀取)；22FDX+ OxRAM (ReRAM) 原型於 2025 釋出，目標 2026 量產。Attopsemi I-fuse™ OTP 於 2021 年公開通過 22FDX 資格（Attopsemi / GF 公開），屬熱輔助電遷移 OTP，不是 22FDX eMRAM。 Industry-first production-ready eMRAM in 2020; 2026 FDX+ AutoPro150 delivers Grade 1 (150°C, 500K cycles, <10ns read); 22FDX+ OxRAM (ReRAM) prototyping available with 2026 volume target. Attopsemi I-fuse™ OTP was publicly qualified on 22FDX in 2021 (Attopsemi / GF public) as heat-assisted-EM OTP, not 22FDX eMRAM.

28SLP & 12LP / 12LP+ FinFET 邊緣 AI 協同開發Edge AI Co-Dev

28SLP 支援成熟 eFlash（含 SST SuperFlash 公開節點）；12LP 與 Everspin 共同開發 MRAM；12LP+ AutoPro150 推進車用 MCU 與邊緣 AI 部署（注意：12LP/12LP+ 為 Bulk FinFET，與 22FDX FD-SOI 物理特性不同）。Actt LogicFlash® 在公開 IP 目錄列於 GF 180–110 nm，屬成熟平面 MTP，不是 12LP FinFET 聲明。 28SLP supports mature eFlash (including public SST SuperFlash nodes); 12LP FinFET MRAM co-developed with Everspin; 12LP+ AutoPro150 targets automotive MCUs (Note: 12LP is FinFET, distinct from 22FDX FD-SOI). Actt LogicFlash® is listed on public IP directories for GF 180–110 nm as mature planar MTP, not a 12LP FinFET claim.

晶圓廠 04 · 三星代工 (SAMSUNG FOUNDRY)FOUNDRY 04 · SAMSUNG FOUNDRY

Samsung Foundry

28FDS (FD-SOI eMRAM) 2019 年起出貨Shipped Since 2019

自 2019 年 3 月宣布商用出貨 eFlash 替代型 eMRAM，寫入快 1000 倍，具備 100 萬次循環與 125°C 10 年保存，支援 5 次 260°C 回流焊。 Commercial shipment of 28FDS eFlash-type eMRAM since March 2019: 1000x faster write, 1M cycles, 10-yr retention at 125°C, surviving 5x 260°C reflows.

14LPP / 8LPU FinFET 車規與射頻 SoCAuto & RF SoC

將 eMRAM 技術自 FD-SOI 延伸至 14nm FinFET 與 8LPU，提供高密度車規 Grade 1 與穿戴式 SoC 支援。 Extended eMRAM to 14nm FinFET and 8LPU, targeting automotive Grade 1 and low-power wearable SoCs.

SF4A (4nm) 與 SF3 / SF2SF4A (4nm) & SF3 / SF2 若另採 OTP 須分流機制If OTP used: split mechanisms 次世代 GAA 奈米片MBCFET GAA Next-Gen

SFF 2024 公布次世代高密度 eMRAM 路線圖，整合於 4nm 車用與 3nm/2nm 環繞閘極奈米片，專注於邊緣 AI 與軟體定義汽車 (SDV)。若同節點另採 0-mask OTP 作信任根或校準，仍須分流閘氧 AntiFuse、擊穿位點未公開的 ZA 類、以及 I-fuse，不得預設單一機制。 SFF 2024 roadmap integrates next-gen eMRAM on SF4A (4nm Auto) and SF3/SF2 MBCFET GAA for edge AI and software-defined vehicles. If the same node also uses 0-mask OTP for RoT or trim, still split gate-oxide AntiFuse, unpublished-site ZA-class, and I-fuse — do not assume one mechanism.

晶圓廠 05 · 特種類比與 BCDFOUNDRY 05 · SPECIALTY ANALOG & BCD

Tower & VIS / PSMC

Tower Y-Flash (0.18um / 65nm BCD)Tower Y-Flash (0.18um / 65nm BCD) 0 光罩 BCD Flash0-Mask BCD Flash

Tower 自研 0 額外光罩 (0 Mask Adders) 單層多晶矽 eFlash/MTP，原生相容 0.18um 與 65nm BCD 製程；支援 150°C~175°C 車規耐溫留存，對高壓 LDMOS 元件擊穿電壓 (BVdss) 零干擾。 Tower proprietary 0-mask single-poly eFlash/MTP natively integrated on 0.18um and 65nm BCD platforms; qualified for 150°C-175°C automotive retention without degrading LDMOS breakdown voltage (BVdss).

世界先進 VIS / 力積電 PSMC (BCD/HV)VIS & PSMC (BCD / HV Ecosystem) 電源微調 MTPPMIC Trim MTP

全面整合億而得 (YMC) 純邏輯多次抹寫 (0-Mask / 1-Mask MTP)，內建專利微型電荷泵，為高壓 PMIC 基準電壓、馬達驅動器偏置與感測器提供出廠即時修調 (Trimming)。 Full integration of YMC 0-mask/1-mask logic MTP with on-chip charge pump, enabling precision trimming for PMIC Vout reference, motor driver offsets, and sensor calibration.

上下游縱向整合生態系UPSTREAM & DOWNSTREAM INTEGRATION ECOSYSTEM

非揮發記憶體上下游縱深整合價值鏈：從晶圓製造到系統信任根與異質封裝 End-to-End NVM Value Chain: From Foundry Fabrication to Root-of-Trust & Heterogeneous Packaging

NVM 選擇並非孤立的位元胞比較，而是涵蓋上游晶圓製程（光罩成本／熱預算）、中游 IP 拓撲（穿隧／電荷泵／物理不可複製性）與下游終端系統（車規 ASIL-D、AI 加速器硬體信任根、無源物聯網）的完整生態協同： NVM selection is never an isolated bitcell decision, but a holistic co-optimization across upstream foundries (mask adders/thermal budget), midstream IP topologies (tunneling/charge pump/PUF), and downstream systems (automotive ASIL-D, AI accelerator HRoT, passive IoT):

01 · 硬體信任根01 · HARDWARE ROOT OF TRUST

PUFsecurity 熵碼科技 PUFsecurity

[上游晶圓][Foundry] TSMC (5nm–55nm) 與 UMC 標準 CMOS 純邏輯製程，0 額外光罩 (0 Mask Adders)。TSMC (5nm-55nm) & UMC standard CMOS logic; 0 mask adders.

[中游 IP][Midstream IP] 利用閘極氧化層微觀隨機量子穿隧變異產生物理不可複製晶片指紋 (NeoPUF)；整合 AntiFuse OTP、NIST SP 800-90B TRNG 與 PUFcc 密碼處理器，天然具備 TEM/FIB 零實體電荷抗性。Harnesses gate oxide quantum tunneling variations for hardware fingerprinting (NeoPUF); pairs with AntiFuse OTP, NIST SP 800-90B TRNG, and PUFcc crypto engine with static TEM immunity.

[下游系統][Systems] AI 邊緣推論加速器模型權重與金鑰保護、車用 ISO 26262 ASIL-D / ISO 21434 安全開機 (Secure Boot)、PSA Certified Level 3 物聯網認證。Edge AI model/key protection, automotive ASIL-D / ISO 21434 secure boot, and PSA Level 3 IoT device credentials.

02 · 電源與感測器微調校準02 · POWER & SENSOR TRIMMING

YMC 億而得微電子 YMC Microelectronics

[上游晶圓][Foundry] 世界先進 (VIS 0.153um/0.18um/0.25um BCD)、力積電 (PSMC)、UMC 等標準邏輯與高壓製程，0-Mask 至 1-Mask。Vanguard (VIS BCD), PSMC, UMC logic and BCD processes; 0-mask to 1-mask adders.

[中游 IP][Midstream IP] 純邏輯 EEPROM / MTP，FN/FN 穿隧機制，1K~100K 抹寫次數；內建專利微型電荷泵，晶片在普通作業電壓下即可完成出廠程式化，免外部高壓測試腳位。Logic EEPROM/MTP with FN/FN tunneling (1K-100K cycles); integrated on-chip charge pump eliminating external high-voltage programming pins.

[下游系統][Systems] 高壓電源管理 IC (PMIC) 基準電壓微調 (Vout Trim)、馬達驅動器偏置修正、Type-C PD 協議控制器、顯示器驅動 Gamma 校準。PMIC Vout voltage trimming, motor driver offset calibration, Type-C PD controllers, and display driver Gamma calibration.

03 · 無源物聯網與超低功耗03 · PASSIVE IOT & ULTRA-LOW POWER

Impinj (AEON 邏輯 NVM) Impinj (AEON Logic NVM)

[上游晶圓][Foundry] TSMC / UMC 純數位邏輯 CMOS 製程，完全不需要額外光罩或外加高壓退火 (0 Mask Adders)。Standard digital CMOS foundry platforms (TSMC/UMC); zero additional mask adders.

[中游 IP][Midstream IP] 單層多晶矽 (Single-Poly) 浮閘架構，極致優化之次微安級 (Sub-µA) 超低功耗感測放大器，兼顧超高感度與可靠保持。Single-poly floating gate topology featuring sub-microampere read sensing current for extreme energy-harvesting budgets.

[下游系統][Systems] 被動式 UHF RFID Tag (Monza 系列)、無電池微弱 RF 能量採集 (Energy Harvesting) 無源物聯網節點與智慧物流防偽追蹤。Passive UHF RFID tags (Monza family), battery-free RF energy-harvesting IoT nodes, and anti-counterfeiting supply chain trackers.

04 · 小晶片與異質系統級封裝04 · CHIPLET & SIP HETEROGENEOUS

Winbond 華邦 & Macronix 旺宏 Winbond & Macronix

[上游晶圓][Foundry] 專用車規與工規 NOR Flash 晶圓工藝 (45nm/28nm)，通過嚴苛之 AEC-Q100 Grade 0 (-40°C ~ +150°C) 認證。Dedicated automotive/industrial NOR Flash processes (45nm/28nm) qualified to AEC-Q100 Grade 0 (-40°C to +150°C).

[中游封裝][Packaging] KGD (Known Good Die) 裸晶堆疊、WLCSP/USON 超小型封裝，透過 Octal SPI / xSPI 介面提供高達 400MB/s 讀取頻寬與就地執行 (XiP)。Known Good Die (KGD), WLCSP/USON packaging, and Octal SPI / xSPI yielding up to 400MB/s bandwidth with execute-in-place (XiP).

[下游系統][Systems] 解決先進節點 (N7/N5/N3 FinFET/GAA) 無法整合嵌入式 Flash 的微縮斷崖，於 ADAS 域控制器、智慧座艙與自駕晶片實現近距極速冷開機 (Instant-On Boot)。Bypasses the advanced FinFET/GAA eFlash scaling cliff, enabling near-die Instant-On boot for ADAS domain controllers and smart cockpits.

05 · 類腦神經運算與嵌入式 RERAM05 · NEUROMORPHIC & EMBEDDED RERAM

Weebit Nano (OxRAM 阻變記憶體) Weebit Nano (OxRAM & CIM)

[上游晶圓][Foundry] SkyWater 130nm CMOS、DB HiTek 130nm BCD 與先進節點拓展評估代工平台，後段 (BEOL) 僅需 2 道額外光罩，熱預算相容標準 CMOS。SkyWater 130nm CMOS, DB HiTek 130nm BCD, and advanced node expansion; requires only 2 BEOL mask adders with standard thermal budget.

[中游 IP][Midstream IP] 金屬氧化物（HfO2/TiN）阻變隨機微絲結構，支援多階電導 (MLC / Analog Conductance Tuning)，整合類比神經形態矩陣乘加運算 (Analog In-Memory Computing, CIM)。Metal-oxide (HfO2/TiN) resistive filaments supporting multi-level analog conductance for analog Computing-in-Memory (CIM) matrix operations.

[下游系統][Systems] 超低功耗邊緣 AI 語音關鍵詞識別 (KWS)、智慧物聯網感測融合、抗輻射工控系統與醫療穿戴式常時在線 (Always-On) 監測。Ultra-low-power edge AI keyword spotting (KWS), smart IoT sensor fusion, radiation-hardened industrial controls, and always-on wearables.

06 · 企業級儲存與斷電保護06 · ENTERPRISE STORAGE & PLP

Everspin (STT-MRAM 與斷電保護) Everspin (STT-MRAM & PLP)

[上游晶圓][Foundry] GlobalFoundries (22FDX / 12LP FinFET) 與 TSMC 代工製造，後段堆疊垂直磁性穿隧接面 (pMTJ)，需 3~4 道額外光罩。Foundry manufacturing at GF (22FDX / 12LP FinFET) and TSMC, stacking perpendicular MTJ (pMTJ) with 3-4 BEOL mask adders.

[中游產品][Product] 獨立式晶片 (1Gb DDR4 / xSPI 介面) 與嵌入式 MRAM 巨集，具備無限次寫入耐久度 (10¹⁰~10¹² 次) 與奈秒級持久寫入速度。Discrete 1Gb DDR4 / xSPI chips and embedded macros offering 10¹⁰-10¹² write endurance and nanosecond-speed persistence.

[下游系統][Systems] 企業級 NVMe SSD 寫入日誌快取、零電容斷電保護 (Capacitor-Free PLP)、CXL 持久性記憶體緩衝區、工業自動化 PLC 與航太抗輻射防護。Enterprise NVMe SSD write journaling, capacitor-free power loss protection (PLP), CXL persistent buffers, industrial PLCs, and rad-hard aerospace.

晶片級實體防竄改安全SILICON-LEVEL ANTI-TAMPER SECURITY

TEM 衰減與差分功耗分析 (DPA) 實體防護責任鏈（非絕對免疫） TEM Attenuation & DPA Side-Channel Layered Defense Chain (Not Absolute Immunity)

① TEM / FIB 可見性與主動屏蔽邊界① TEM / FIB Visibility & Active Shielding Boundary
AntiFuse 崩潰微絲約 3–8nm，局域包裹於標準閘極氧化層中，無表面形貌變化，較吹斷級 eFuse 熔斷空洞具備極高的物理逆向成本。I-fuse 公開為非爆破熔絲，IEEE JEDS 2019 稱編程狀態較難以 SEM 目視判讀，仍非絕對免疫。但需注意：非揮發微絲／熔絲狀態為永久性物理結構，位元單元本身無法「單週期自我清除」；系統級防禦依賴開機時將密鑰載入揮發性快取 (Volatile Shadow RAM)，當頂層主動金屬屏蔽 (Active Metal Mesh) 偵測到 FIB 微探針或開路時，由控制器觸發暫存器之單週期即時零化 (Zeroization)。此為物理衰減結合系統聯防，非位元單元絕對免疫。 AntiFuse filaments are ~3–8nm localized inside standard gate oxide without surface topological changes, imposing high reverse-engineering barriers compared to blow-class eFuse voids. I-fuse is published as a non-explosive fuse; IEEE JEDS 2019 reports programmed state as hard to visually detect by SEM — still not absolute immunity. Note: the physical filament or fuse state is irreversible and cannot self-zeroize. System security relies on shadowing keys into volatile RAM at boot; when the active top-metal mesh detects FIB probing, the controller triggers instantaneous register zeroization. Hardware attenuation + architectural co-defense, not bitcell-level absolute immunity.

② 互補差動讀取（DPA/CPA 衰減邊界）② Complementary Differential Read (DPA/CPA Attenuation Boundary)
成對互補差動讀取（A=HRS, B=LRS）使兩條位元線同時抽取電流，瞬態總功耗近似常數 I_total = I_HRS + I_LRS，可大幅衰減一階差分功耗 (DPA) 與相關功耗 (CPA) 訊跡。但面對高階差分功耗 (Higher-order DPA) 與局域電磁輻射分析 (EMA)，晶圓佈線不對稱性仍可能洩漏側信道特徵。因此，完備防禦必須落實多層責任鏈：位元層差動對消 + 控制器層隨機遮罩 (Masking) 與時脈抖動 + 密碼引擎擾碼。 Complementary differential read pairs (A=HRS, B=LRS) draw current simultaneously on both bitlines (I_total = I_HRS + I_LRS), significantly attenuating first-order DPA and CPA traces. However, against higher-order DPA and localized EMA probes, layout asymmetry can still leak side-channel signatures. Complete protection mandates a layered defense chain: bitcell-level current cancellation + controller-level algorithmic masking/jitter + cryptographic engine bus scrambling.

05 · 晶片級讀取拓樸05 · ARCHITECTURAL READ TOPOLOGIES

四大晶片級讀取模式：感測邊界、面積開銷與側信道衰減全景 Four Architectural Read Modes: Sense Margins, Area Overhead & Side-Channel Attenuation

非揮發性記憶體（OTP、MTP、eFlash、MRAM）在微架構層級的讀取拓樸，直接決定了晶片的感測餘裕（Sense Margin）、PVT 溫漂容忍度、位元胞面積開銷（Area Overhead）與一階差分功耗分析（DPA/CPA）側信道防護邊界。下圖展示四種抽象讀取電路拓樸：從單端參考感測，到僅可能針對明確模型涵蓋的單點失效提供有限容錯的互補差動冗餘架構（不可視為零缺陷認證）。 At the microarchitectural level, the non-volatile memory read topology dictates the sense margin, PVT drift resilience, bitcell area overhead, and first-order DPA/CPA side-channel attenuation boundary. The architectural sketches below classify four read topologies — from single-ended reference sensing to differential+redundant schemes that may tolerate modeled single-point faults (not zero-defect certification). 教學邊界：固定 dB、0-ppm、175°C 或 ASIL/CC 等級僅能在具名產品／FMEDA 出現，不得由架構圖直接推出。 Teaching boundary: Fixed dB, 0-ppm, 175°C, or ASIL/CC tiers require named products/FMEDA — not inference from cartoons alone.

物理紀律：PHYSICAL DISCIPLINE: 嚴格正交直角電路拓樸 · 100% 杜絕對角線與視差錯位 Strict 90° Orthogonal Schematics · Zero Diagonal Parallax 實證連結：EVIDENCE LINK: 記憶體微觀讀取物理 ↗ Memory Read Physics ↗ & 一手差動衰減總帳 (V07) ↗ Primary Ledger V07 ↗

01 · 單端讀取 (Single-Ended) 01 · Single-Ended Read

1T 單元 · 外部參考源 1T Cell · External Ref

運作原理：單一實體位元胞（1-Cell）的讀取電流或電壓直接輸入感測放大器正端，與參考單元、能隙或其他片上產生器提供的固定參考（Vref/Iref）比較以判定 0 或 1。 Operating Principle: A single physical bitcell current or voltage feeds into the positive sense amplifier input, compared against a fixed reference (Vref/Iref) from a reference cell, bandgap, or other on-chip generator to resolve 0 or 1.

單元面積AREA 1.0×（基準）1.0× (MIN)

參考基準REF SOURCE 參考單元／Vref 產生器Ref cell / Vref generator

一階 DPA 衰減1ST DPA ATTEN 無衰減（易受攻擊）None (Vulnerable)

優勢：矽面積開銷最低，位元線路由最為簡潔，讀取延遲低且功耗最小。Pros: Minimal silicon area footprint, simplest bitline routing, lowest latency and read power.
局限：感測餘裕受製程、電壓與溫度（PVT）溫漂劇烈影響；資料為 0 與 1 的電流差異極大，一階 DPA/CPA 訊跡直觀可辨。Cons: Sense margin suffers from PVT drift; large current difference between 0 and 1 creates intuitive first-order DPA/CPA traces.
典型應用：高密度類比 Trim 校準碼、晶圓 ID（Wafer ID）、非安全敏感的標準產品配置暫存器。Target Applications: High-density analog trim calibration, Wafer ID, non-sensitive standard configuration registers.

02 · 單端並聯冗餘 (Redundant Read) 02 · Redundant Single-Ended Read

≥2 並聯 · 外部參考源 ≥2 Parallel · External Ref

運作原理：在同一條位元線上並聯兩個或更多同極性實體單元（Parallel Replicas），共同注入感測放大器輸入端並與 Vref 比較。只要其中一個單元成功導通即可建立狀態。 Operating Principle: Two or more same-polarity physical cells are connected in parallel to drive the sense amplifier input against Vref. Programmed state is established as long as any single parallel element conducts.

單元面積AREA 2.0× ~ 3.0×

參考基準REF SOURCE 外部能隙基準 (Bandgap)External Bandgap

一階 DPA 衰減1ST DPA ATTEN 無衰減（同極性疊加）None (Same Polarity)

優勢：極大程度容忍氧化層擊穿隨機未完全軟失效（Soft Breakdown）或製造隨機缺陷，大幅改善晶圓成品率（Yield）。Pros: Highly tolerant of incomplete dielectric soft breakdown and random defects, significantly boosting yield.
局限：實體面積開銷翻倍；仍然受全域 Vref 溫漂綁定；同極性並聯對一階 DPA 側信道並無衰減，甚至放大電流峰值。Cons: Doubles silicon area; still bound to global Vref drift; same-polarity parallel elements do not attenuate first-order DPA traces.
典型應用：記憶體內建自我修復（BISR）備援重映射暫存器、車規級一次性開機安全旗標。Target Applications: Built-in self-repair (BISR) remap fuseboxes, automotive-grade boot flags.

03 · 互補差動讀取 (Differential Read) 03 · Complementary Differential Read

BL 對 /BL · 零外部參考 BL vs /BL · Zero External Ref

運作原理：每個邏輯位元由成對的互補實體單元編碼（真值單元與補值單元必有一通一斷）。差動感測放大器直接量測 BL 與 /BL 之電壓差，完全自洽比較，無需外部參考電壓。 Operating Principle: Each logical bit is encoded across a complementary cell pair (one programmed, one unprogrammed). A differential sense amp compares BL against /BL directly, eliminating external references.

單元面積AREA 2.0× ~ 2.2×

參考基準REF SOURCE 自洽比較（零外部 Vref）Self-Referenced (0 Vref)

一階 DPA 衰減1ST DPA ATTEN 定性共模抑制（具名案例）Qualitative CMRR (named cases)

優勢（原理）：互補對可抑制部分共模漂移；雙側電流抽取有助於降低一階 DPA 訊跡 — 實際 dB 與溫漂免疫需具名巨集量測。Pros (principle): Complementary pairs attenuate some common-mode drift; dual-rail current draw can reduce first-order DPA traces — actual dB and drift immunity need named macro data.
局限：位元胞與解碼路由佔用約 2 倍面積；面對高階 DPA 或局域電磁輻射（EMA），佈局微觀不對稱仍需搭配頂層屏蔽網與演算法遮罩。Cons: Doubles cell and routing area; higher-order DPA or localized EMA can exploit physical layout asymmetry unless paired with top metal shields.
典型應用：AES-256 根金鑰儲存、PKI 設備身分憑證、安全開機第一階段向量（Stage 1 Boot Vector）。Target Applications: AES-256 cryptographic root keys, PKI device certificates, Stage-1 secure boot trust anchors.

04 · 互補差動並聯冗餘 (Diff + Redundant) 04 · Differential + Redundant Read

4T 四元陣列 · 教學冗餘 · 零外部參考 4T Cell · Teaching redundancy · Zero-Ref

運作原理：互補真值軌與補值軌各自配置 ≥2 個單元並聯，並以差動放大器對消自洽感測 — 針對已建模的單點失效可能提供容錯；未建模的共通路徑、短路或匹配失效仍可能影響讀取。 Operating Principle: True and complementary rails each use ≥2 parallel bitcells into a differential sense amplifier — may tolerate modeled single-cell faults; unmodeled common-path, short, or mismatch failures can still affect readout.

單元面積AREA 4.0× ~ 4.5×

參考基準REF SOURCE 自洽比較（零外部 Vref）Self-Referenced (0 Vref)

一階 DPA 衰減1ST DPA ATTEN 冗餘＋差動（具名案例）Redundant + diff (named cases)

優勢（原理）：差動對加上並聯冗餘可針對已建模的單點失效提供容錯；不等同 0-ppm、175°C 認證或 ASIL/EAL 資格 — 需具名 FMEDA／產品條件。Pros (principle): Differential pairs plus parallel redundancy can tolerate modeled single-point faults — not equivalent to 0-ppm, 175°C certification, or ASIL/EAL qualification without named FMEDA/product bounds.
局限：面積開銷最高（≥4 倍單元面積），編程時間與燒錄電流預算增加。Cons: Highest area penalty (≥4x single cell footprint); longest programming time and write energy budget.
典型應用（需另證）：高可靠車規／金融 RoT 等可能採用類似拓樸；ASIL 等級與 CC 評估須對應具名產品與系統整合。Example domains (evidence required): Automotive/financial RoT designs may use similar topologies; ASIL tier and CC evaluation require named products and system integration.

NVM 四大晶片級讀取模式工程維度對比矩陣 Four Silicon Read Modes Engineering Trade-Off Matrix
架構維度Metric	01 · 單端讀取 (Single)01 · Single-Ended	02 · 單端冗餘 (Redundant)02 · Redundant	03 · 互補差動 (Differential)03 · Differential	04 · 差動＋冗餘 (Diff+Red)04 · Diff + Redundant
實體單元數 / bitPhysical Cells / bit	1 Cell	≥2 Cells (同極性並聯)≥2 Cells (Parallel)	2 Cells (互補對稱)2 Cells (Complementary)	≥4 Cells (雙軌各並聯)≥4 Cells (Dual-Rail Parallel)
外部參考源依賴External Ref Requirement	依賴帶隙 Vref/IrefRequires Bandgap Vref/Iref	依賴帶隙 Vref/IrefRequires Bandgap Vref/Iref	0 外部依賴 (對內互比)Zero External Ref (Self-Referenced)	0 外部依賴 (對內互比)Zero External Ref (Self-Referenced)
感測餘裕與溫漂抗性Sense Margin & PVT Drift	受製程/電壓/溫度漂移牽引Prone to PVT drift	單元缺陷容錯提升，溫漂仍存Higher defect margin; reference drift persists	差動自洽，大幅抵消全域溫漂Self-referencing; common-mode drift cancelled	極致強韌（最高感測餘裕）Maximum Margin (Ultra-robust)
相對面積開銷Silicon Area Overhead	1.0× (基準基準線)1.0× (Baseline)	約 2.0× ~ 2.5×~2.0× to 2.5×	約 2.0× ~ 2.2×~2.0× to 2.2×	約 4.0× ~ 4.5×~4.0× to 4.5×
一階 DPA/CPA 側信道1st-Order DPA/CPA Leak	無衰減（訊號直觀可辨）No attenuation (Direct signature)	無衰減（同向充放電）No attenuation (Common charge curve)	高衰減（雙軌同時抽載對消）High attenuation (Complementary draw cancellation)	極高衰減（對消 + 冗餘平滑）Extreme attenuation (Cancellation + Smoothing)
隨機缺陷與未擊穿容錯Random Defect Tolerance	無（單元軟失效即報廢）None (Single point of failure)	高（任一單元導通即成立）High (Tolerates single cell failure)	中等（需確保兩單元均良好）Moderate (Requires both cells functional)	最高（容忍單側單元隨機失效）Maximum (Tolerates single-side defects)
適用架構等級Recommended Tier	類比 Trim、晶圓 ID、配置位元Analog trim, Wafer ID, config bits	BISR 修復、工規韌體指標BISR repair, industrial boot flags	晶片硬體信任根、AES 金鑰Hardware Root of Trust, AES keys	高可靠 RoT 候選（須具名 FMEDA／產品）High-assurance RoT candidate (named FMEDA/product)

架構工程註記與引證邊界：Engineering Notes & Claim Boundaries: 上述拓樸均為晶片系統架構級抽象模型，非特定單一具名商標 IP 之專屬資料手冊。差動讀取對 DPA/CPA 之衰減效能係基於雙軌對稱抽載的一階電流互補物理（參考 Synopsys 公開架構與本站一手證據總帳 V07 ↗）。面對高階差分功耗（Higher-order DPA）與局域微探針電磁輻射（EMA），必須配合頂層主動金屬屏蔽網（Active Metal Mesh）與演算法遮罩（Algorithmic Masking）落實多層縱深防禦。 The four topologies represent system architecture-class abstract models rather than a proprietary datasheet from a specific IP vendor. Differential DPA/CPA attenuation stems from first-order complementary current draw physics (refer to Synopsys public disclosure & Hub Primary Evidence Ledger V07 ↗). Against higher-order DPA and localized EMA, silicon architects must deploy layered defenses incorporating active top metal shields and algorithmic masking.

06 · 架構師決策管線06 · ARCHITECT PIPELINE

三步收斂：架構師 NVM 決策簽核管線 Three-Stage Architectural NVM Selection Pipeline

STEP 01 關卡 1 · 契約審查 GATE 1 · AUDIT

狀態契約與生命週期審查 State Contract Audit

區分不可變身分 (Immutable ID)、校準邊界 (Calibration) 與韌體代碼。若資料僅需工廠寫入或偶發修補，優先評估 0-mask OTP，並分流 AntiFuse（CFX 教學為閘氧崩潰；Floadia ZA 為介電層永久導通、擊穿位點未公開）、I-fuse 熱輔助電遷移、以及浮閘 OTP；不得預設「OTP = AntiFuse」。韌體 OTA 再評估 Logic MTP（FN/FN、CHI/FN、TwinBit Schottky 三分流）或 eFlash。 Distinguish immutable identity from firmware. For write-once or bounded patch models, evaluate 0-mask OTP and split AntiFuse (CFX teaching default is GOX; Floadia ZA is dielectric conduction with unpublished breakdown site), I-fuse heat-assisted EM, and floating-gate OTP — do not default “OTP = AntiFuse”. Firmware OTA then evaluates Logic MTP (FN/FN vs CHI/FN vs TwinBit Schottky) or eFlash.

簽核準則：零開銷數據保持 · 匯流排零洩漏 CRITERION: 0-Overhead Retention · Zero Bus Leak

STEP 02 關卡 2 · 預算評估 GATE 2 · BUDGET

製程微縮與熱預算可行性 Process Node & Thermal Budget

檢查晶圓代工廠 PDK。若節點小於 28nm，平面 SST／單層浮閘 MTP 通常不可行；仍須核對 0-mask 例外：TwinBit Gen-2 公開至 22 nm、I-fuse 公開資格含 GF 22FDX、ZA 公開至 sub-10 nm。eFlash 不要一律 8–12 道光罩：G1 為 +2–3、G2 為 +4（開發中）。其餘再評估 3~5 道 BEOL 導入 MRAM。 Verify foundry PDK roadmap. Beyond 28nm, planar SST and single-poly FG MTP are usually out; still check 0-mask exceptions: TwinBit Gen-2 public to 22 nm, I-fuse public qualification includes GF 22FDX, ZA public to sub-10 nm. Do not treat every eFlash as 8–12 masks: G1 is +2–3 and G2 is +4 (in development). Then decide between 3–5 BEOL adders (MRAM) and remaining 0-mask logic NVM.

簽核準則：0 光罩邏輯相容性 · ≤450°C 熱預算安全 CRITERION: 0-Mask Logic Compatibility · ≤450°C Safe

STEP 03 關卡 3 · 實體驗證 GATE 3 · CHECKLIST

實體驗證與防禦簽核 Physical Verification Checklist

依據 AEC-Q100 Grade 0 規範驗證 175°C 結溫高溫工作壽命 (HTOL 1000h)、早期失效率 (ELFR 2400 顆 c=0) 與高溫數據保持烘烤 (Retention Bake)，並評估 TEM 逆向防護邊界，確保微絲歐姆接觸無熱漂移退化。 Qualify per AEC-Q100 Grade 0 specifications at 175°C Tj HTOL 1000h, early life failure rate (ELFR 2,400 units c=0), and data retention bake, alongside TEM anti-tamper boundary analysis to assess ohmic-drift risk (architecture-class; HTOL/ELFR depend on target qualification).

簽核準則：TEM 物理衰減（非免疫）· 175°C 結溫車規 Grade 0 檢核 CRITERION: TEM Attenuation (Not Immunity) · Grade 0 Class Checklist @ 175°C Tj